The Software/Hardware Implementation and Research Architecture (SHIRA) is a C to hardware toolchain developed by the Computer Architecture Research Group (CARG) of the University of Ottawa. The framework and algorithms to generate the hardware from an Intermediate Representation (IR) of the C code is needed. This dissertation presents the conceiving, design, and development of a module that generates the hardware for custom instructions identified by specialized SHIRA components without the need for any user interaction. The module is programmed in Java and takes a Data Flow Graph (DFG) as an IR for input. It then generates VHDL code that targets the Altera FPGAs. It is possible to use separate components for each operation or to set a maximum number for each component which leads to component reuse and reduces chip area use. The performance improvement of the generated code is compared to using only the processor’s standard instruction set.

Uma sequencia de vídeo pode ser adquirida de forma progressiva ou entrelaçada. No padrão de codificação de vídeo H.264/AVC os campos de uma imagem entrelaçada podem ser codificados em modo frame (campos top e bottom entrelaçados) ou em modo field (campos top e bottom agrupados separadamente). Quando a escolha é adaptativa para cada par de macro blocos a codificação é chamada de Macroblock Adaptive Frame- Field (MBAFF). Inovações na predição inter-quadro do H.264/AVC contribuíram significantemente para a performance do padrão alcançar o dobro da taxa de compressão do seu antecessor (ITU, 1994), ao custo de um grande aumento de complexidade computacional do CODEC. Dentro da predição inter-quadro, o bloco de compensação de movimento (MC) é responsável pela reconstrução de um bloco de pixels. No decodificador apresentado em (BONATTO, 2012) está integrada uma solução em hardware para o MC que suporta a maior parte do conjunto de ferramentas do perfil Main do H.264/AVC. A compensação de movimento pode ser dividida em predição de vetores e processamento de amostras. No processamento de amostras é realizada a interpolação e a ponderação de amostras. O módulo de ponderação de amostras, ou predição ponderada, utiliza fatores de escala para escalonar as amostras na saída do MC. Isso é muito útil quando há esvanecimento no vídeo. Inicialmente este trabalho apresenta um estudo do processo de compensação de movimento, segundo o padrão de codificação de vídeo H.264/AVC. São abordadas todas as ferramentas da predição inter-quadro, incluindo o tratamento de vídeo entrelaçado e todos os possíveis modos de codificação para o mesmo. A seguir é apresentada uma arquitetura em hardware para a predição ponderada do MC. Esta arquitetura atende o perfil main do H.264/AVC, que prevê a decodificação de imagens frame, field ou MBAFF. A arquitetura apresentada é baseada no compensador de movimento contido no decodificador apresentado em (BONATTO, 2012), que não tem suporte a predição ponderada e a vídeo entrelaçado. A arquitetura proposta é composta por dois módulos: Scale Factor Prediction (SFP) e Weighted Samples Prediction (WSP) . A arquitetura foi desenvolvida em linguagem VHDL e a simulação temporal mostrou que a mesma pode decodificar imagens MBAFF em tempo real @60i. Dessa forma, tornando-se uma ferramenta muito útil ao desenvolvimento de sistemas de codificação e decodificação em HW. Não foi encontrada, na literatura atual, uma solução em hardware para compensação de movimento do padrão H.264/AVC com suporte a codificação MBAFF. / A video sequence can be acquired in a progressive or interlaced mode. In the video coding H.264/AVC standard an interlaced picture can be encoded in frame mode (top and bottom fields interlaced) or field mode (top and bottom fields combined separately). When the choice for each pair of macro-blocks coding is adaptive, it is called Macroblock Adaptive Frame-Field (MBAFF). The innovations in the inter-frame prediction of H.264/AVC contributed significantly to the performance of the standard that achieved twice the compression ratio of its predecessor (ITU, 1994), at the cost of a large increase in computational complexity of the CODEC. In the inter-frame prediction, the motion compensation (MC) module is responsible for the reconstruction of a pixel's block. In the decoder shown in (BONATTO 2012) an integrated hardware solution to the MC is included which can decode most of the H.264/AVC main profile tools. The motion compensation can be divided into motion vectors prediction and sample processing. In the sample processing part, samples interpolation and weighting are performed. The weighted samples prediction module uses scale factors to weight the samples for generating the output pixels. This is useful in video fading. Initially, this work presents a study of the motion compensation process, according to the H.264/AVC standard. It covers all of inter-frame prediction tools, including all possible coding modes for interlaced video. A hardware architecture for the weighted samples prediction of MC is shown next. It is in compliance with the main profile of H.264/AVC standard, therefore it can decode frame, field and MBAFF pictures. The architecture presented is based on the motion compensator used in the (BONATTO, 2012) decoder, which does not support the weighted prediction and interlaced video. The purposed architecture is composed by two modules: Scale Factor Prediction (SFP) and Weighted Samples Prediction (WSP). The hardware implementation was described using VHDL and the timing simulation has shown that it can decode MBAFF pictures in real time @60i. Therefore, this is an useful tool for hardware CODEC development. Similar hardware solution for H.264/AVC weighted prediction that supports MBAFF coding was not found is previous works.

The thesis deals with the analysis and the reception of the freely available signals of the navigation satellites in the L1 and E1 bands of the GPS and Galileo systems. The described signal reception sections include the process of the acquisition, the carrier frequency and phase synchronization and tracking, the spreading code phase tracking, the signal demodulation and the channel decoding. The simulation of the entire receiver is performed in MATLAB. The deeply analyzed signal reception component is the one responsible for the carrier phase and frequency synchronization and tracking. In that case, more methods and their comparison are usually listed. The signal reception component, which is responsible for the carrier phase and frequency tracking and the spreading code phase tracking, is also implemented in FPGA.

This thesis describes a conceptual design of touchless fingerprint sensor and design, implementation and testing of its firmware, which is a composition of hardware implemented in VHDL and a program implemented in C. Result of this thesis can be used as the first step of building an industrial solution.

The master's thesis deals with design of a solution for time synchronization in computer networks that is a crucial problem of many network applications. Based on analysis of protocols for time synchronization, PTP protocol was chosen as an appropriate candidate. The thesis describes the implementation of the design for a special network interface card and demonstrates features of the solution in several tests. A part of the solution processing precise timestamps was implemented in FPGA chip on the network card while PTP messages are processed in a software application. Values of configurable parameters of the application were determined based on analysis of the network card properties and results of particular tests. It was achieved accuracy in order of tens of nanoseconds.

This work deals with the design and implementation of a hardware unit that is capable of playing MPEG-1 Layer III files, compliant with ISO/IEC 11172-3. There are given the benefits of using the MP3 format and principles that make it possible to compress the size of the resulting music recordings. The file format and all parts of the header are thoroughly studied as well as the method of encoding information. The process of the data decoding is divided into several consecutive, more or less discrete functional units and these units are designed and described in a hardware description language VHDL. There are also discussed features of FPGA chips - programmable gate arrays. Those are used for physical realization of the MP3 player. A development board is selected, including such an FPGA chip and other resources that allow synthesis of the entire circuit and playback in real time.

The thesis deals with the issue of implementing a PCI interface controller utilizing the FPGA technology. It describes the design and the implementation of a PCI communication card, which is used to control servomotors in cutting machines. In the thesis, the steps taken in designing and implementation of hardware and software parts of the communication card are discussed. The result of the thesis is a functional piece of equipment, which is to be manufactured.

This thesis contains introduction to PMS motor control using development board ZedBoard with Xilinx Zynq-7000 SoC. After that, there is a description of development environment Vivado and other modules. Finally, it contains description or created modules in Vivado environment which were combined together with peripheral drivers to demonstrate field oriented motor control algorithm of small PMS motor.

This diploma thesis is focused on the design of IP blocks for thermal camera. This termal camera is intended for plant research. The main part of the thermal camera is an infrared detector that detects a frequency in the range of 8 – 14 m. The analogue signal obtained is modified and subsequently digitized. The detector also includes a Peltier device which is designed for both detector cooling and heating, and is controlled by an external signal. The MicroZed development board implements IP blocks. The thermal camera is designed to be controlled from the MicroZed board. Device analysis is first described from the theoretical part to the design of IP blocks.

This work deals with COMBO2 card interconnect and memory devices testing. In the beginning of the paper, some existing testing algorithms for interconnect and RAM memories testing are introduced. This work is devoted to proposal of generic architecture for interconnect and memory devices testing. The proposed architecture is optimized for FPGA implementation.