Global ETD Search

451	Implementation of a Program Address Generator in a DSP processor / Implementering av en Programadress generator i en DSP processor Waltersson, Roland January 2003 (has links) <p>The purpose of this thesis is to construct a"Program Address Generator"(PAG) to a 24-bit Harvard type, RISC DSP processor using the VHDL language. The PAG is a part of the program control unit, and should consist of the following units: </p><p>A system stack for storing jump and loop information. A program counter, a status register, a stack pointer, an operating mode register and two registers called loop address and loop counter register, to support hardware loops. </p><p>The PAG handles the fetch stage of the processor pipeline, and should handle instructions such as the jump, subroutine jump, return from subroutine/interrupt and loop instructions, among others. </p><p>The PAG was successfully designed, and its function verified through extensive tests, where common combinations of ASM instructions were tested. Files for automated testing was created, to support easy testing if only small changes are applied to the PAG.</p> Electronics DSP Program Control Unit VHDL fetch pipeline branch hazard RISC stack program counter status register Elektronik Electronics Elektronik
452	Design of a Finite-Impulse Response filter generator / Konstruktion av en FIR filter generator Broddfelt, Michel January 2003 (has links) <p>In this thesis a FIR filter generator has been designed. The program generates FIR filters in the form of VHDL-files. Four different filter structures have been implemented in the generator, Direct Form (DF), Differential Coefficients Method (DCM), polyphase filters and (2-by-2) filters. </p><p>The focus of the thesis was to implement filter structures that create FIR filters with as low power consumption and area as possible. </p><p>The generaterator has been implemented i C++. The C++ program creates text-files with VHDL-code. The user must then compile and synthesize the VHDL-files. The program uses an text-file with the filter coefficients as input.</p> Electronics FIR filter generator DF DCM polyphase 2-by-2 VHDL low-power small area Elektronik Electronics Elektronik
453	Power Estimation of High Speed Bit-Parallel Adders / Effektestimering av snabba bitparallella adderare Åslund, Anders January 2004 (has links) <p>Fast addition is essential in many DSP algorithms. Various structures have been introduced to speed up the time critical carry propagation. For high throughput applications, however, it may be necessary to introduce pipelining. In this report the power consumption of four different adder structures, with varying word length and different number of pipeline cuts, is compared. </p><p>Out of the four adder structures compared, the Kogge-Stone parallel prefix adder proves to be the best choice most of the time. The Brent-Kung parallel prefix adder is also a good choice, but the maximal throughput does not reach as high as the maximal throughput of the Kogge-Stone parallel prefix adder.</p> Electronics Power simulations Pipelining Adder Ripple carry Conditional sum Brent-Kung Kogge-Stone Parallel prefix VHDL DSP Elektronik Electronics Elektronik
454	Automating IEEE 1500 wrapper insertion Huss, Niklas January 2009 (has links) <p>Integrated circuits (ICs) are becoming increasingly complex, which leadsto long design and development times. Designing ICs in a modular fashionis efficient to shorten design and development times. Due to imperfection inIC manufacturing, all ICs are tested. An IC designed in a modular fashioncan be tested in a modular manner. To enable modular test, the IEEE 1500std has been developed to enable isolation and access of modules. Whilethe IEEE 1500 std is adopted, there is yet no commercial tool available.</p><p>In this thesis we have (1) developed an IEEE 1500 std wrapper and (2)included it in a design flow based on a commercial tool, and developed scriptto automate the process. Given a module in VHDL, our design automationautomatically makes synthesis, scan insertion, test generation (ATPG), andwrapper insertion. We have applied the design flow to several benchmarksand through simulation verified the correctness.</p> VHDL Python Wrapper Insertion Computer science Datavetenskap
455	Development of a FPGA-based True Random Number Generator for Space Applications Shanmuga Sundaram, Prassanna January 2010 (has links) <p>Random numbers are required for cryptographic applications such as IT security products, smart cards etc. Hardwarebased random number generators are widely employed. Cryptographic algorithms are implemented on FieldProgrammable Gate Arrays (FPGAs). In this work a True Random Number Generator (TRNG) employed for spaceapplication was designed, investigated and evaluated. Several cryptographic requirements has to be satisfied for therandom numbers. Two different noise sources was designed and implemented on the FPGA. The first design wasbased on ring oscillators as a noise source. The second design was based on astable oscillators developed on a separatehardware board and interfaced with the FPGA as another noise source. The main aim of the project was to analyse theimportant requirement of independent noise source on a physical level. Jitter from the oscillators being the source forthe randomness, was analysed on both the noise sources. The generated random sequences was finally subjected tostatistical tests.</p> True random number generator cryptography random jitter FPGA VHDL ring oscillator astable oscillator statistical tests Electrical engineering Elektroteknik
456	Klass-D Förstärkare Johansson, Jonas, Lazarian, Arten January 2007 (has links) <p>Syftet med högskoleavhandlingen var att konstruera en klass-D förstärkare för audio med en DDXi-2161 krets från Apogee. Förstärkaren har en digital stereoingång för I²S-format. Digitalisering av en analog audiosignal sker med codec-kretsen WM8731 från Wolfson. För att möjliggöra implementering av funktioner för digital signalbehandling av audiosignalen ingår en FPGA-krets från Altera i systemet. Gränssnitten mellan codec-kretsen och FPGA:n samt FPGA:n och klass-D förstärkaren är beskrivna med VHDL och implementerade i FPGA:n. Klass-D förstärkaren har byggts upp på ett två-lagers mönsterkort. Ett utvecklingskort från ALTERA (DE2) med codec-krets och FPGA har använts. Resultaten visar goda möjligheter att konstruera en klass-D förstärkare med bra ljud och låg effektförbrukning.</p> FPGA DDXi-2161 Digital Förstäkare Klass-D förstäkare VHDL Altera Quartus II Mentor Graphics DDX® Electrical engineering Elektroteknik
457	Automatic Generation of Hardware for Custom Instructions Necsulescu, Philip I 12 August 2011 (has links) The Software/Hardware Implementation and Research Architecture (SHIRA) is a C to hardware toolchain developed by the Computer Architecture Research Group (CARG) of the University of Ottawa. The framework and algorithms to generate the hardware from an Intermediate Representation (IR) of the C code is needed. This dissertation presents the conceiving, design, and development of a module that generates the hardware for custom instructions identified by specialized SHIRA components without the need for any user interaction. The module is programmed in Java and takes a Data Flow Graph (DFG) as an IR for input. It then generates VHDL code that targets the Altera FPGAs. It is possible to use separate components for each operation or to set a maximum number for each component which leads to component reuse and reduces chip area use. The performance improvement of the generated code is compared to using only the processor’s standard instruction set. FPGA Instruction Set Extension ISE Custom Instruction Automatic Hardware Generation Assisted Hardware Generation VHDL Embedded Systems Custom Hardware
458	Automatic Generation of Hardware for Custom Instructions Necsulescu, Philip I 12 August 2011 (has links) The Software/Hardware Implementation and Research Architecture (SHIRA) is a C to hardware toolchain developed by the Computer Architecture Research Group (CARG) of the University of Ottawa. The framework and algorithms to generate the hardware from an Intermediate Representation (IR) of the C code is needed. This dissertation presents the conceiving, design, and development of a module that generates the hardware for custom instructions identified by specialized SHIRA components without the need for any user interaction. The module is programmed in Java and takes a Data Flow Graph (DFG) as an IR for input. It then generates VHDL code that targets the Altera FPGAs. It is possible to use separate components for each operation or to set a maximum number for each component which leads to component reuse and reduces chip area use. The performance improvement of the generated code is compared to using only the processor’s standard instruction set. FPGA Instruction Set Extension ISE Custom Instruction Automatic Hardware Generation Assisted Hardware Generation VHDL Embedded Systems Custom Hardware
459	Development of a FPGA-based True Random Number Generator for Space Applications Shanmuga Sundaram, Prassanna January 2010 (has links) Random numbers are required for cryptographic applications such as IT security products, smart cards etc. Hardwarebased random number generators are widely employed. Cryptographic algorithms are implemented on FieldProgrammable Gate Arrays (FPGAs). In this work a True Random Number Generator (TRNG) employed for spaceapplication was designed, investigated and evaluated. Several cryptographic requirements has to be satisfied for therandom numbers. Two different noise sources was designed and implemented on the FPGA. The first design wasbased on ring oscillators as a noise source. The second design was based on astable oscillators developed on a separatehardware board and interfaced with the FPGA as another noise source. The main aim of the project was to analyse theimportant requirement of independent noise source on a physical level. Jitter from the oscillators being the source forthe randomness, was analysed on both the noise sources. The generated random sequences was finally subjected tostatistical tests. True random number generator cryptography random jitter FPGA VHDL ring oscillator astable oscillator statistical tests Electrical engineering Elektroteknik
460	Implementation of a Program Address Generator in a DSP processor / Implementering av en Programadress generator i en DSP processor Waltersson, Roland January 2003 (has links) The purpose of this thesis is to construct a"Program Address Generator"(PAG) to a 24-bit Harvard type, RISC DSP processor using the VHDL language. The PAG is a part of the program control unit, and should consist of the following units: A system stack for storing jump and loop information. A program counter, a status register, a stack pointer, an operating mode register and two registers called loop address and loop counter register, to support hardware loops. The PAG handles the fetch stage of the processor pipeline, and should handle instructions such as the jump, subroutine jump, return from subroutine/interrupt and loop instructions, among others. The PAG was successfully designed, and its function verified through extensive tests, where common combinations of ASM instructions were tested. Files for automated testing was created, to support easy testing if only small changes are applied to the PAG. Electronics DSP Program Control Unit VHDL fetch pipeline branch hazard RISC stack program counter status register Elektronik Electronics Elektronik

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