No description available.

No description available.

Lattice-Reduction has become a popular way of improving the performance of MIMO detectors. However, developing an efficient high-throughput VLSI implementation of LR has been a major challenge in the literature. This thesis proposes a hardware-optimized version of the popular LLL algorithm that reduces its complexity by 70% and achieves a fixed runtime while maintaining ML diversity. The proposed algorithm is implemented for 4x4 MIMO systems and uses a novel pipelined architecture that achieves a fixed low processing latency of 40 cycles, resulting in a fixed throughput that is independent of the channel correlation. The proposed LR core, fabricated in 0.13um CMOS, is the first fabricated and tested LR ASIC implementation in the literature. Test results show that the LR core achieves a maximum clock rate of 204 MHz, yielding a throughput of 510 Mbps, thus satisfying the aggressive throughput requirements of emerging 4G wireless standards, such as IEEE-802.16m and LTE-Advanced.

Lattice-Reduction has become a popular way of improving the performance of MIMO detectors. However, developing an efficient high-throughput VLSI implementation of LR has been a major challenge in the literature. This thesis proposes a hardware-optimized version of the popular LLL algorithm that reduces its complexity by 70% and achieves a fixed runtime while maintaining ML diversity. The proposed algorithm is implemented for 4x4 MIMO systems and uses a novel pipelined architecture that achieves a fixed low processing latency of 40 cycles, resulting in a fixed throughput that is independent of the channel correlation. The proposed LR core, fabricated in 0.13um CMOS, is the first fabricated and tested LR ASIC implementation in the literature. Test results show that the LR core achieves a maximum clock rate of 204 MHz, yielding a throughput of 510 Mbps, thus satisfying the aggressive throughput requirements of emerging 4G wireless standards, such as IEEE-802.16m and LTE-Advanced.

UWB is a promising technology for short-range high-rate wireless applicationa.It is able to providemaximal 480Mbps data-rate at a distance of 2 meters in realisticindoormulti-path environments. UWB technology is widely applied to the next generation WPAN as well as the wireless accessof consumer electronics at home. Recently, Multi-Band OFDM based UWB technology proposed by WiMedia has been selected as the international standard by ISO. In China, a new transmission architecture based on Dual-Carrier OFDM technology is adopted as UWB standard draft. Comparing to MB-OFDM based UWB system, DC-OFDM based UWB system has multiple advantages, like more spectrum resource,lower requirements on devices, etc. Besides, it is compatiblewith existing MB-OFDM based UWB technology. Therefore, DC-OFDM based UWB is more flexible. Synchronizationis the first step atthe receiver digital baseband, which is of tremendous importance in any wireless communication systems. The performance of synchronization directly determines whether the receiver can pick up radio signals correctly or not, whether the baseband modules can fulfill the digital signal processing effectively or not. The synchronization process in OFDM system can be briefly divided into two parts: symbol timing and frequency synchronization. Symbol timing serves to judge the starting position of OFDM symbolsafter considering the impact of multi-path fading channel.While the frequency synchronization estimates the multiple imperfections in analog front-end signal processing and make proper compensation. This thesis puts the emphasis on synchronization issues in DC-OFDM based UWB systems. We are the first to analyze the synchronization algorithm as well as the hardware implementation method tailored for DC-OFDM based UWB system. We also present the VLSI implementation result for synchronization module. The thesis consists of symbol timing and frequency synchronization. Regarding on the symbol timing, we analyze the impact of several synchronization errors inOFDM system. After that, we divide the synchronization process into four modulesby functionality: packet detection, coarse timing, TFC detection and fine timing. The internal parameters in each moduleare determined by system simulations. In the aspect of algorithm development, we adopt the joint auto-correlation and cross-correlation method to meet the requirements of UWB system in different indoor multi-path environments, and therefore achieve the robustness. In the aspect of hardware implementation, we put the attention on the structure of some key modules in symbol timing and their VLSI implementation result, such as auto-correlator, cross-correlator, real-number divider, etc. Regarding on the frequency synchronization, we first investigate the multiple analog front-end imperfections in OFDM system, like CFO, SFO and I/Q imbalance, and present their mathematics models respectively in DC-OFDM based UWB system.After that, we analyze the performance degradation in OFDM system due to these non-ideal effects by the metric of EVM. RF designer can build the connection between mismatching parameters and performance degradation by referring to the analysis. Hence, theRF designer is able to traceout the outline of system design. In the aspect of algorithm development, we explore the intrinsic character of I/Q imbalancewhich causes the image interference. Then, we design a set of new training sequences based on phase rotation and give the corresponding estimation algorithm.The simulation result shows that the new training sequence is able to obtain the diversity message introduced by I/Q imbalance and therefore achieve the diversity gain during demodulation process. In order to deal with the challenging situation where multiple analog front-end imperfections co-exist, we propose a joint estimation and compensation scheme. In the aspect of hardware implementation, we present the hardware structure of CFO estimation and compensation module catered for DC-OFDM based UWB system, with the emphasis on CORDIC unit that is responsible for triangle calculations. The VLSI implementation result shows that the proposed CFO estimation and compensation module satisfies the timing and resource requirements in DC-OFDM based UWB system. In the last, we present the prospective research area in 60-GHz applications. It includes multiplenon-ideal impairments, like phase noise, non-linear power amplification, DC offset, ADCs mismatch, etc. It is even more challenging to develop joint estimation and compensation scheme for these non-ideal effects.

No description available.

No description available.

No description available.

Η μετάδοση δεδομένων µέσω ασύρματων δικτύων αποτελεί ένα από τα σημαντικότερα αντικείμενα μελέτης στον χώρο των τηλεπικοινωνιών τα τελευταία χρόνια. Λόγω του μεγάλου όγκου δεδομένων που απαιτείται για μετάδοση μέσα σε πολύ μικρό χρονικό διάστημα, απαιτείται η εφαρμογή όσο το δυνατόν αποδοτικότερης κωδικοποίησης και διαμόρφωσης, σκοπεύοντας παράλληλα στην επίτευξη μικρής κατανάλωσης ισχύος και ταυτόχρονα υψηλού throughput. Η παρούσα διπλωματική εργασία πραγματεύεται τη μελέτη, σχεδίαση και την υλοποίηση της αρχιτεκτονικής ενός OFDM συστήματος, βασισμένο στις προδιαγραφές που ορίζει το πρότυπο IEEE802.11. Το πρότυπο αυτό επιλέχθηκε, καθώς τυγχάνει ευρείας αποδοχής, όσον αφορά τη μετάδοση δεδομένων σε ασύρματα δίκτυα. Στα πλαίσια της διπλωματικής παρουσιάζονται εξομοιώσεις και μετρήσεις για την εύρεση των κατάλληλων χαρακτηριστικών και του τύπου των φίλτρων που χρησιμοποιούνται σε ένα OFDM σύστημα, ενώ εισάγονται δύο νέες αρχιτεκτονικές του τμήματος κατασκευής του OFDM συμβόλου, καθώς και τα αποτελέσματα της σύνθεσης αυτών. Ιδιαίτερη βαρύτητα δίνεται στη σχεδίαση και την υλοποίηση των αρχιτεκτονικών αυτών με σκοπό την ενσωμάτωσή τους σε συσκευές FPGA. / Transmission of data through wireless networks is one of the most important aspects in the study telecommunications systems. The large volume of data that needs to be transmitted in a very small time interval has resulted in the need to make the system more efficient while increasing the throughput. This has been accomplished through more efficient coding, reduction of the power consumption and through the use of modulation. This masters thesis deals with the study, design and implementation of the typical OFDM system architecture, based on the standard IEEE802.11. This standard was chosen because of its wide acceptance and use regarding transmission of data in wireless networks. The thesis details the adjustments and measurements needed for determining suitable characteristics and the types of filters required in an OFDM system. Additionally two new OFDM system architectures arte introduced aiming at reducing the overall power consumption and the complexity of the formulae used for symbol construction. Particular importance is given in the designing and the implementation of these architectures regarding their incorporation in FPGA devices.

The efficient high-throughput VLSI implementation of Soft-output MIMO detectors for high-order constellations and large antenna configurations has been a major challenge in the literature. This thesis introduces a novel Soft-output K-Best scheme that improves BER performance and reduces the computational complexity significantly by using three major improvement ideas. It also presents an area and power efficient VLSI implementation of a 4x4 64-QAM Soft K-Best MIMO detector that attains the highest detection throughput of 2 Gbps and second lowest energy/bit reported in the literature, fulfilling the aggressive requirements of emerging 4G standards such as IEEE 802.16m and LTE-Advanced. A low-complexity and highly parallel algorithm for QR Decomposition, an essential channel pre-processing task, is also developed that uses 2D, Householder 3D and 4D Givens Rotations. Test results for the QRD chip, fabricated in 0.13um CMOS, show that it attains the lowest reported latency of 144ns and highest QR Processing Efficiency.