Given, on the one hand, the poor results obtained by Peruvian children in the national and international reading assessments. And on the other hand, the increased investment intechnology for schools in the country, this study aimed to develop and test an online tool to improve reading comprehension. In order to do this, the reading comprehension strategies and vocabulary activities from the research-based digital environment ICON were adapted to design the platform LEO. A total of 88 fifth graders from urban middle-to-low-income private schools from Lima participated in this quasi-experimental study, which involved acontrol group and a treatment group that participated in a 12-week teacher-mediated digital intervention. All participants were administered reading and vocabulary assessments pre and post intervention. Results revealed that students who participated in the intervention achieved higher comprehension scores for narrative texts and higher vocabulary scores than those of the control group. / Frente a los bajos resultados que los niños peruanos obtienen en las pruebas nacionales e internacionales de comprensión de lectura y tomando en consideración el aumento de inversión en tecnología en las instituciones educativas del país, el presente estudio buscó desarrollar y evaluar una herramienta virtual para mejorar la comprensión de lectura. Para ello, se adaptaron las estrategias de comprensión de lectura y ejercicios de vocabulario del entorno virtual ICON y se diseñó la plataforma LEO. Un total de 88 estudiantes de quinto grado de primaria, provenientes de colegios privados de nivel socioeconómico medio-bajo de Lima Metropolitana, participaron en este estudio cuasi-experimental, con un grupo control y un grupo que participó en la intervención digital a lo largo de 12 semanas. Todos los participantes fueron evaluados utilizando pruebas de entrada y salida de comprensión de lectura y vocabulario. Los resultados revelaron que los estudiantes que interactuaron con la plataforma LEO obtuvieron resultados significativamente más altos en la comprensión de textos narrativos y vocabulario luego de finalizada la intervención, respecto a sus puntajes al inicio de la misma y también en comparación con el grupo que no empleó la plataforma.

En la actualidad, bajo la coyuntura actual que vivimos a causa de la pandemia COVID-19, el uso de servicios freelance por parte de personas naturales y por los distintos emprendimientos se ha incrementado, debido a que el mundo se ha digitalizado y existe un importante potencial de crecimiento en los servicio digitales, sobre todo para potenciar perfiles empresariales en redes sociales o para fines personales. Considerando ello, nuestro proyecto se basa en la creación de una plataforma web con presencia en redes sociales que desempeñará el rol de nexo entre freelancers y usuarios, que requieran de sus servicios digitales, enfocándonos en el público ubicado en Lima Metropolitana. El objetivo principal de esta plataforma es que ambos segmentos vivan una experiencia agradable, rápida, eficiente y segura, que satisfaga sus necesidades en el canal digital; con la visión de impulsar la generación de ingresos, de manera sostenible y formal. Para la sustentación de este proyecto se desarrollaron diversos experimentos que permitieron validar la existencia de la necesidad detectada, las posibles soluciones y el plan que se armó para las cuatro semanas de concierge del proyecto. Los resultados que obtuvimos de los experimentos, nos llevaron a comprender la importancia de validar el segmento de socios clave y el canal de atención y comunicación con nuestros clientes; así como validar las intenciones de compra y las ventas realizadas. Descritas las líneas anteriores, colocamos a disposición de los lectores el presente trabajo de investigación para que sirva como guía para futuros proyectos e ideas de negocio, que resulten sostenibles en el tiempo, siguiendo un espíritu innovador en cada etapa. / The present research work consists of the development of a web platform that connects freelancers with users, the purpose is to see the feasibility of digitizing this industry from new tactics and tools of connection between these users. The objective of this platform is to seek to offer a fast and efficient experience, which allows you to meet your needs as individuals. With the vision of facilitating income generation in the wake of this pandemic, in a sustainable and formal way. To support this project, several experiments were developed to validate the existence of a common need or problem and a business model that provides an immediate solution. The results of these concierges will provide to ascertain the hypothesis of the strategies on which this project is based. In the last part of the document, you will be able to appreciate the financing plan of the business structure, as well as the development of an integrated marketing plan, social responsibility purposes and a financial analysis that determines and estimates the degree of success of the project. Finally, for the development of each part of the support of the project, internal and external change factors that may significantly affect the company were taken into account, such as political uncertainty and the global crisis due to COVID-19. To this end, applicable strategies are developed for each scenario as part of a contingency plan, as well as various proposals that directly or indirectly influence key processes for the project, which allows to know the level of acceptance of the business idea. / Tesis

To capture the market in the field of SoC, the companies have to launch their product ahead of their competitors. Virtual platforms allow the building and testing of software before the hardware is available, so the hardware and software development can take place in parallel and reduce the time to market. A virtual platform is used to perform faster simulation. It simulates the functionality of the hardware rather than modeling timing details. In SystemC based simulators, the loosely timed model allows the SystemC threads to run multiple cycles before they synchronize with other threads in the system by a method called temporal decoupling. The amount of time for which the threads can run ahead is called the global quantum. Increasing the quantum can cause a thread to run for a longer time, thus reducing the context switching overhead. This increases the simulation speed, but at the cost of accuracy. In this work, the effects of temporal decoupling in SystemC based virtual platforms is evaluated by simulating three different variants of virtual platforms, each for two target ASIC platforms. The goal is to check whether varying the temporal decoupling affects the performance. The global quantum value is varied in steps and data is collected for the effective quantum. The quantum utilization is then calculated to see the share of global quantum actually used during a simulation. To see how changing the global quantum affects the performance, the simulation times for various quantum values are also measured and the reduction in context switches is also calculated. Two variants showed reduction in context switches upto 96% when compared to the values at lowest measured quantum and the quantum utilization is found to be higher for these variants compared to the first variant. The simulation time decreased when the global quantum was increased, up to a certain value of the global quantum. Some test cases also failed at higher quantum values. It is observed that the global quantum can be used as an accuracy parameter in a simulator, provided the coupling in the simulator between the SystemC threads is low enough, so that the effective quantum follows an increase in the global quantum. / För att fånga marknaden inom området SoC måste företag lansera sinq produkter före sina konkurrenter. De virtuella plattformarna gör det möjligt att bygga och testa mjukvara innan hårdvaran finns tillgänglig, så hårdvaru- och mjukvaruutvecklingen kan ske parallellt och minska ledtiden. En virtuell plattform används för att utföra snabbare simulering. Den simulerar hårdvarans funktionalitet snarare än att modellera tidsinformation. I SystemC-baserade simulatorer tillåter den löst tidskopplade modellen SystemC-trådarna att köra en förutbestämd tid innan de synkroniseras med andra trådar i systemet. På detta sätt blir trådarna tidsmässigt frikopplade från varandra. Den tid som trådarna kan köra framåt kallas det globala kvantat. Att öka kvantat kan leda till att trådarna exekverar längre och därmed minskar antalet trådbyten. Detta ökar simuleringshastigheten men på bekostnad av noggrannhet. I detta arbete utvärderas effekterna av tidsmässig frikoppling i SystemC-baserade virtuella plattformer genom att simulera tre olika varianter av virtuella plattformar, vardera för två olika ASIC plattformar. Målet är att kontrollera om variationen i den tidsmässiga frikopplingen påverkar prestandan. Det globala kvantumvärdet varieras i steg och data samlas in för det effektiva kvantat. Kvantum-utnyttjandet beräknas sedan för att se hur stor del av det globala kvantat som faktiskt används under en simulering. För att se hur en förändring av det globala kvantat påverkar prestandan mäts också simuleringstiderna för olika kvantum-värden och reduktionen i antalet trådbyten beräknas. Två varianter uppvisade en minskning av antalet trådbyten upp till 96% jämfört med lägsta uppmätta kvantumvärdet och kvantum-utnyttjandet visade sig vara högre för dessa varianter jämfört med den första varianten. Simuleringstiden visade en minskning när det globala kvantat ökades, upp till ett visst värde. Vissa testfall misslyckades vid högre kvantumvärden. Detta visar att globala kvantat kan användas som en noggrannhetsparameter i en simulator, förutsatt att simulatorn har tillräckligt löst kopplade trådar, så att det effektiva kvantat ökar när det globala kvantat ökar.

In recent years, developers have wanted to design more complex and advanced embedded processors. The feasibility of developed processors must be verified before the actual application. However, the process of verification always needs high costs and time. Quick Emulator (QEMU), a virtual platform emulator, can help in this situation. It can emulate different processors and hardware environments and build a unique platform according to the designers wishes. Many people have used QEMU to emulate advanced Reduced Instruction Set Computing (RISC) processors (like ARM) or the X86 architectures. Still, there is little research on RISC-V processors. Therefore, studying the QEMU to emulate the RISC-V processor is important. This thesis aims to evaluate the performance of the RISC-V processor using QEMU. Ten different benchmarks are designed, and their results are compared to reflect the performance of the RISC-V as well as the simulator. These results provide a reference when these benchmarks are run on the RISC-V processor that is on the actual hardware development board. / De senaste åren har utvecklarna alltid velat utveckla mer komplexa och avancerade funktioner på inbyggda utvecklingskort. Men de nya funktionerna måste verifieras innan man gör kretskortet. Å andra sidan så kostar verifieringsprocessen mycket tid och pengar. Quick Emulator (QEMU), en virtuell plattformsemulator, kan hjälpa till för att lösa detta problem. Den kan emulera olika processorer och hårdvarumiljöer och bygga en unik plattform allt enligt designernas önskemål. Många människor har använt QEMU för att emulera avancerade Reduced Instruction Set Computing (RISC)-processorer (som ARM), eller X86-arkitekturerna, men det finns mycket lite forskning om RISC-V processorer. Därför är det viktigt att studera QEMU för att emulera RISC-V-processorn. Denna avhandling syftar till att utvärdera prestandan för RISC-V processorer genom att använder QEMU. Tio olika benchmarks konstrueras för att användas för att spegla prestandan hos processorn såväl som simulatorn. Dessa resultat kan sedan användas som referens när benchmarken körs på de RISC-V-processorer som finns på det aktuella hårdvaruutvecklingskortet.

A complexidade dos sistemas integrados em chips bem como a arquitetura de processadores comerciais vem crescendo dramaticamente nos últimos anos. Com isto, a dificuldade de avaliarmos a suscetibilidade às falhas em decorrência da incidência de partículas espaciais carregadas nestes dispositivos cresce com a mesma taxa. Este trabalho apresenta uma análise comparativa da susceptibilidade à erros de software em um microprocessador embarcado ARM Cortex-A9 single core de larga escala comercial, amplamente utilizado em aplicações críticas, executando um conjunto de 11 aplicações desenvolvidas para um ambiente bare metal e para o sistema operacional Linux. A análise de soft errors é executada por injeção de falhas na plataforma de simulação OVPSim juntamente com o injetor OVPSim-FIM, capaz de sortear o momento e local de injeção de uma falha. A campanha de injeção de falhas reproduz milhares de bit-flips no banco de registradores do microprocessador durante a execução do conjunto de benchmarks que possuem um comportamento de código diverso, desde dependência de fluxo de controle até aplicações intensivas em dados. O método de análise consiste em comparar execuções da aplicação onde falhas foram injetadas com uma execução livre de falhas. Os resultados apresentam a taxa de falhas que são classificadas em: mascaradas (UNACE), travamento ou perda de controle de fluxo (HANG) e erro nos resultados (SDC). Adicionalmente, os erros são classificados por registradores, separando erros latentes por sua localização nos resultados e por exceções detectadas pelo sistema operacional, provendo novas possibilidades de análise para um processador desta escala. O método proposto e os resultados obtidos podem ajudar a orientar desenvolvedores de software na escolha de diferentes arquiteturas de código, a fim de aprimorar a tolerância à falhas do sistema embarcado como um todo. / The complexity of integrated system on-chips as well as commercial processor’s architecture has increased dramatically in recent years. Thus, the effort for assessing the susceptibility to faults due to the incidence of spatial charged particles in these devices has growth at the same rate. This work presents a comparative analysis of soft errors susceptibility in the commercial large-scale embedded microprocessor ARM Cortex-A9 single core, widely used in critical applications, performing a set of 11 applications developed for a bare metal environment and the Linux operating system. The soft errors analysis is performed by fault injection in OVPSim simulation platform along with the OVPSim-FIM fault injector, able to randomly select the time and place to inject the fault. The fault injection campaign reproduces thousands of bit-flips in the microprocessor register file during the execution of the benchmarks set, with a diverse code behavior ranging from control flow dependency to data intensive applications. The analysis method is based on comparing applications executions where faults were injected with a fault-free implementation. The results show the error rate classified by their effect as: masked (UNACE), crash or loss of control flow (HANG) and silent data corruption (SDC); and by register locations. By separating latent errors by its location in the results and exceptions detected by the operating system, one can provide new better observability for a large-scale processor. The proposed method and the results can guide software developers in choosing different code architectures in order to improve the fault tolerance of the embedded system as a whole.

A complexidade dos sistemas integrados em chips bem como a arquitetura de processadores comerciais vem crescendo dramaticamente nos últimos anos. Com isto, a dificuldade de avaliarmos a suscetibilidade às falhas em decorrência da incidência de partículas espaciais carregadas nestes dispositivos cresce com a mesma taxa. Este trabalho apresenta uma análise comparativa da susceptibilidade à erros de software em um microprocessador embarcado ARM Cortex-A9 single core de larga escala comercial, amplamente utilizado em aplicações críticas, executando um conjunto de 11 aplicações desenvolvidas para um ambiente bare metal e para o sistema operacional Linux. A análise de soft errors é executada por injeção de falhas na plataforma de simulação OVPSim juntamente com o injetor OVPSim-FIM, capaz de sortear o momento e local de injeção de uma falha. A campanha de injeção de falhas reproduz milhares de bit-flips no banco de registradores do microprocessador durante a execução do conjunto de benchmarks que possuem um comportamento de código diverso, desde dependência de fluxo de controle até aplicações intensivas em dados. O método de análise consiste em comparar execuções da aplicação onde falhas foram injetadas com uma execução livre de falhas. Os resultados apresentam a taxa de falhas que são classificadas em: mascaradas (UNACE), travamento ou perda de controle de fluxo (HANG) e erro nos resultados (SDC). Adicionalmente, os erros são classificados por registradores, separando erros latentes por sua localização nos resultados e por exceções detectadas pelo sistema operacional, provendo novas possibilidades de análise para um processador desta escala. O método proposto e os resultados obtidos podem ajudar a orientar desenvolvedores de software na escolha de diferentes arquiteturas de código, a fim de aprimorar a tolerância à falhas do sistema embarcado como um todo. / The complexity of integrated system on-chips as well as commercial processor’s architecture has increased dramatically in recent years. Thus, the effort for assessing the susceptibility to faults due to the incidence of spatial charged particles in these devices has growth at the same rate. This work presents a comparative analysis of soft errors susceptibility in the commercial large-scale embedded microprocessor ARM Cortex-A9 single core, widely used in critical applications, performing a set of 11 applications developed for a bare metal environment and the Linux operating system. The soft errors analysis is performed by fault injection in OVPSim simulation platform along with the OVPSim-FIM fault injector, able to randomly select the time and place to inject the fault. The fault injection campaign reproduces thousands of bit-flips in the microprocessor register file during the execution of the benchmarks set, with a diverse code behavior ranging from control flow dependency to data intensive applications. The analysis method is based on comparing applications executions where faults were injected with a fault-free implementation. The results show the error rate classified by their effect as: masked (UNACE), crash or loss of control flow (HANG) and silent data corruption (SDC); and by register locations. By separating latent errors by its location in the results and exceptions detected by the operating system, one can provide new better observability for a large-scale processor. The proposed method and the results can guide software developers in choosing different code architectures in order to improve the fault tolerance of the embedded system as a whole.

Submitted by Fernando Souza (fernandoafsou@gmail.com) on 2017-07-31T15:56:31Z No. of bitstreams: 1 arquivototal.pdf: 3333792 bytes, checksum: af8dec04eb92a0f889d3af32060c5218 (MD5) / Made available in DSpace on 2017-07-31T15:56:31Z (GMT). No. of bitstreams: 1 arquivototal.pdf: 3333792 bytes, checksum: af8dec04eb92a0f889d3af32060c5218 (MD5) Previous issue date: 2017-04-04 / This research describes and analyzes a pedagogical experience developed at the Escola de Referência em Ensino Médio Padre Antônio Barbosa Júnior - EREMPABJ, involving the use of the Virtual Platform Ecaths as a support to face-to-face teaching in basic education. The main objective of this work is to describe the virtual environment of the Ecaths platform and the feasibility of its tools for the teaching and learning of the English language and the possibilities of building the digital literacy of the students. The theoretical framework used was based on the conceptions of Rapaport (2008); Holden (2009); Paiva (2012) and Carvalho and Braga (2012) for the teaching of the English Language; The literacy concepts of Soares (2002) and Kleiman (1995), digital literacy, Buzato, (2006), Coscarelli (2014, 2016,Kenski (2015), Lemos and Matos (2016); ICT in education, Matos and Rodrigues (2013), Moran (2000, 2013), Prensky (2001), Toktov (2003) among others. The reflection about the pedagogical possibilities adopted for the case study generated data and analyzes capable of contributing not only to the improvement of the studied discipline, but also to subsidize any other teacher who wishes to use the virtual environment of the Ecaths platform in other contexts of teaching and learning. In order to reach the objective, in the course of the research, written tests and questionnaires were carried out to generate the data. In presenting the data, we used a qualitative analysis combined with elements of quantitative analysis, complemented by the observations of the researcher-teacher. At the end, we see that the experience is closely related to the socio-interactionist theories that consider the interaction, be it with the subject or the object, a premise for effective learning of both the structural and functional aspects of the English language, as well as the enabling of digital literacy. / Esta pesquisa descreve e analisa uma experiência pedagógica desenvolvida na Escola de Referência em Ensino Médio Padre Antônio Barbosa Júnior - EREMPABJ, envolvendo o uso da Plataforma Virtual Ecaths como apoio ao ensino presencial na educação básica. O objetivo central deste trabalho é descrever o ambiente virtual da plataforma Ecaths e as viabilidades de suas ferramentas para o ensino e aprendizagem da língua inglesa e as possibilidades de construção do letramento digital dos discentes. O referencial teórico utilizado baseou-se nas concepções de Rapaport (2008); Holden (2009); Paiva (2012) e Carvalho e Braga (2012) para o ensino da Língua Inglesa; os conceitos de letramento de Soares (2002) e Kleiman (1995), letramento digital, Buzato, (2006); Coscarelli (2014, 2016); Kenski (2015), Lemos e Matos (2016); TIC em educação: Matos e Rodrigues (2013); Moran (2000, 2013); Prensky (2001); Toktov (2003) entre outros. A reflexão em torno das possibilidades pedagógicas adotadas para o estudo de caso gerou dados e análises capazes de contribuir não apenas para o aprimoramento da disciplina estudada, como também para subsidiar qualquer outro professor que deseje utilizar o ambiente virtual da plataforma Ecaths em outros contextos de ensino e de aprendizagem. Para atingir o objetivo, no decorrer da pesquisa, foram realizados testes escritos e questionários para a geração dos dados. Ao apresentar os dados utilizou-se uma análise qualitativa combinada com elementos de análise quantitativa, complementada pelas observações do professor-pesquisador. Ao término, vislumbramos que a experiência realizada está estreitamente relacionada com as teorias sociointeracionistas que consideram a interação, seja com o sujeito ou com o objeto, premissa para aprendizagem efetiva tanto dos aspectos mais estruturais quanto funcionalistas da língua inglesa, bem como possibilitadora de letramento digital.

A complexidade dos sistemas integrados em chips bem como a arquitetura de processadores comerciais vem crescendo dramaticamente nos últimos anos. Com isto, a dificuldade de avaliarmos a suscetibilidade às falhas em decorrência da incidência de partículas espaciais carregadas nestes dispositivos cresce com a mesma taxa. Este trabalho apresenta uma análise comparativa da susceptibilidade à erros de software em um microprocessador embarcado ARM Cortex-A9 single core de larga escala comercial, amplamente utilizado em aplicações críticas, executando um conjunto de 11 aplicações desenvolvidas para um ambiente bare metal e para o sistema operacional Linux. A análise de soft errors é executada por injeção de falhas na plataforma de simulação OVPSim juntamente com o injetor OVPSim-FIM, capaz de sortear o momento e local de injeção de uma falha. A campanha de injeção de falhas reproduz milhares de bit-flips no banco de registradores do microprocessador durante a execução do conjunto de benchmarks que possuem um comportamento de código diverso, desde dependência de fluxo de controle até aplicações intensivas em dados. O método de análise consiste em comparar execuções da aplicação onde falhas foram injetadas com uma execução livre de falhas. Os resultados apresentam a taxa de falhas que são classificadas em: mascaradas (UNACE), travamento ou perda de controle de fluxo (HANG) e erro nos resultados (SDC). Adicionalmente, os erros são classificados por registradores, separando erros latentes por sua localização nos resultados e por exceções detectadas pelo sistema operacional, provendo novas possibilidades de análise para um processador desta escala. O método proposto e os resultados obtidos podem ajudar a orientar desenvolvedores de software na escolha de diferentes arquiteturas de código, a fim de aprimorar a tolerância à falhas do sistema embarcado como um todo. / The complexity of integrated system on-chips as well as commercial processor’s architecture has increased dramatically in recent years. Thus, the effort for assessing the susceptibility to faults due to the incidence of spatial charged particles in these devices has growth at the same rate. This work presents a comparative analysis of soft errors susceptibility in the commercial large-scale embedded microprocessor ARM Cortex-A9 single core, widely used in critical applications, performing a set of 11 applications developed for a bare metal environment and the Linux operating system. The soft errors analysis is performed by fault injection in OVPSim simulation platform along with the OVPSim-FIM fault injector, able to randomly select the time and place to inject the fault. The fault injection campaign reproduces thousands of bit-flips in the microprocessor register file during the execution of the benchmarks set, with a diverse code behavior ranging from control flow dependency to data intensive applications. The analysis method is based on comparing applications executions where faults were injected with a fault-free implementation. The results show the error rate classified by their effect as: masked (UNACE), crash or loss of control flow (HANG) and silent data corruption (SDC); and by register locations. By separating latent errors by its location in the results and exceptions detected by the operating system, one can provide new better observability for a large-scale processor. The proposed method and the results can guide software developers in choosing different code architectures in order to improve the fault tolerance of the embedded system as a whole.

En la actualidad, bajo la coyuntura actual que vivimos a causa de la pandemia COVID-19, el uso de servicios freelance por parte de personas naturales y por los distintos emprendimientos se ha incrementado, debido a que el mundo se ha digitalizado y existe un importante potencial de crecimiento en los servicio digitales, sobre todo para potenciar perfiles empresariales en redes sociales o para fines personales. Considerando ello, nuestro proyecto se basa en la creación de una plataforma web con presencia en redes sociales que desempeñará el rol de nexo entre freelancers y usuarios, que requieran de sus servicios digitales, enfocándonos en el público ubicado en Lima Metropolitana. El objetivo principal de esta plataforma es que ambos segmentos vivan una experiencia agradable, rápida, eficiente y segura, que satisfaga sus necesidades en el canal digital; con la visión de impulsar la generación de ingresos, de manera sostenible y formal. Para la sustentación de este proyecto se desarrollaron diversos experimentos que permitieron validar la existencia de la necesidad detectada, las posibles soluciones y el plan que se armó para las cuatro semanas de concierge del proyecto. Los resultados que obtuvimos de los experimentos, nos llevaron a comprender la importancia de validar el segmento de socios clave y el canal de atención y comunicación con nuestros clientes; así como validar las intenciones de compra y las ventas realizadas. Descritas las líneas anteriores, colocamos a disposición de los lectores el presente trabajo de investigación para que sirva como guía para futuros proyectos e ideas de negocio, que resulten sostenibles en el tiempo, siguiendo un espíritu innovador en cada etapa. / The present research work consists of the development of a web platform that connects freelancers with users, the purpose is to see the feasibility of digitizing this industry from new tactics and tools of connection between these users. The objective of this platform is to seek to offer a fast and efficient experience, which allows you to meet your needs as individuals. With the vision of facilitating income generation in the wake of this pandemic, in a sustainable and formal way. To support this project, several experiments were developed to validate the existence of a common need or problem and a business model that provides an immediate solution. The results of these concierges will provide to ascertain the hypothesis of the strategies on which this project is based. In the last part of the document, you will be able to appreciate the financing plan of the business structure, as well as the development of an integrated marketing plan, social responsibility purposes and a financial analysis that determines and estimates the degree of success of the project. Finally, for the development of each part of the support of the project, internal and external change factors that may significantly affect the company were taken into account, such as political uncertainty and the global crisis due to COVID-19. To this end, applicable strategies are developed for each scenario as part of a contingency plan, as well as various proposals that directly or indirectly influence key processes for the project, which allows to know the level of acceptance of the business idea. / Trabajo de investigación

Muchas de las actividades que realiza diariamente una persona, están expuestas a diferentes factores de riesgos negativos. Lamentablemente, varios de estos logran concretarse causando grandes pérdidas. Estos hechos amenazan a una persona en su integridad, su vida, su interés y su propiedad. Es por ello, que se deben buscar los medios que mermen el origen de estos eventos o al menos que ayuden a que no sea una gran carga para quien lo padezca. A este mecanismo hoy en día se le llama seguro, el cual es brindado por varias empresas de nuestro país. Con el tiempo estas organizaciones se han convertido en un medio que garantiza la reparación de un siniestro en su totalidad o en gran parte. Es por ello, que cada vez más personas van adquiriendo estos servicios. Dentro de este contexto, las compañías de seguros locales ofrecen distintos tipos de productos y servicios. El seguro vehicular es uno de estos y son los más solicitados porque el índice de siniestralidad en la capital frente a robos, choques y daños materiales en el sector automotriz han ido incrementándose en los últimos años (APESEG, 2019). Por esta razón, la atención de los siniestros se vuelve cada vez más complicada de controlar ya que la comunicación e información compartida entre una central de siniestro vehicular, el procurador y el asegurado se vuelve inexacta y poco confiable debido a la misma naturaleza del servicio y la premura de su atención. El presente estudio aborda las tecnologías y herramientas actuales que se usan en los procesos operativos de la atención de un siniestro vehicular en una empresa que brinda servicios para compañías de seguros. Se empieza mostrando el modelo tradicional de operación de una central de siniestros y su interacción con el procurador y asegurado, luego se presentan las tecnologías y modelos más actuales para que dicha atención sea más oportuna y eficaz, en otras palabras, una mejora en los procesos. Las tendencias van hacia el uso de herramientas de software basadas en plataformas móviles de uso extensivo y su integración con los otros sistemas, el cual es un soporte tecnológico ideal para los servicios que ofrecen las compañías de seguros. / Many of the activities that a person performs daily are exposed to different negative risk factors. Unfortunately, several of them fail to materialize causing great losses. These events threaten a person's integrity, his life, his interest, and his property. For this reason, means should be sought to reduce the origin of these events or at least help prevent them from being a big problem for those who suffer from it. Nowadays this mechanism is called insurance, which is provided by several companies in our country. Over time, these organizations have become a way of guaranteeing the repair of a loss in whole or in part. That is why more and more people are acquiring these services. The local insurance companies offer different types of products and services. Auto insurance is one of them and they are the most requested because the accident rate in the capital due to theft, collisions and material damage has been increasing in recent years (APESEG, 2019). For this reason, request of claims becomes increasingly complicated to control due to the communication and information shared between a vehicle emergency center, the vehicle attorney and the insured becomes inaccurate and unreliable due to the very nature of the service and the urgency of its attention. This study studies the current technologies and tools that are used in the operational processes of the attention of a vehicular accident in a company that provides services for insurance companies. It begins by showing the traditional operating model of a vehicle emergency center and its interaction with the vehicle attorney and the insured. Then the most current technologies and models are presented to make a customer service more effective, in other words, an improvement in processes. The trends are directed to the use of software tools based on widely used mobile platforms and their integration with other systems, which constitutes an ideal technological support for the services offered by insurance companies. / Tesis