In this thesis, high-voltage nitrile-based electrolytes for lithium ion batteries were investigated. The electrolytes were composed of nitrile, dinitrile, and vinylene carbonate (VC) as an additive. Scanning electron microscopy showed the change of surface morphology of electrodes. The chemical compositions of the solid electrolyte interface were characterized by high resolution X-ray photo electron spectroscopy (HR-XPS). We found that the optimal ratio of dinitrile to nitrile is 6 to 4 by volume in terms of electrochemical performances. 5wt% VC as the additive has the enhanced electrochemical performances. The oxidation potential of the nitrile-based electrolytes can reach to 5.7 V. The discharge capacity of the Li||LiFePO4 cell with the nitrile-based electrolyte is about 80 mAhg-1 at a charge/discharge rate of 5 C under 30 oC, and its discharge efficiency after 100 cycles still keeps 94.35%.

Two different topics associated with their respective applications are proposed in this thesis. The first topic is the implementation of a 6-T SRAM cell using dual threshold voltage transistors and low power quenchers. We proposed a SRAM cell with dual threshold voltage transistors. The advantages of such a design is to reduce the access time and maintain data retention at the same time. Besides, the unwanted oscillation of the output data lines caused by large currents is reduced by adding two back-to-back quenchers. The second topic is focused on the implementation of a programmable PLL-based frequency multiplier. Using the method of a phase-locked loop and a programmable divisor to implement a frequency multiplier. ¢Ï synchronous clock signal can be generated by the proposed design. It can also be used in wireless communication systems, e.g. local oscillators.

We developed low voltage wide swing second generation current conveyors(CCII) with the application to a insensitive Butterworth second-order low-pass filter. All circuits are designed using the parameters of TSMC 1P4M 0.35um process. The minimum supply voltage of CCII(1) circuit is |Vtp|+3Vod. The supply voltage of CCII(2) circuit is |Vtp|+2Vod. The voltage swing of the CCIIs are almost rail to rail.

When the shaft current passes through the bearing under lubrication condition, the arc often occurs and the pitting can be observed on the surface of bearing. Consequently, the life of bearing is shortened. The pitting resulting from discharge is dependent upon the shaft voltage, the oil film thickness, and the insulation of lubricant. To simulate the pitting, the dynamic pitting tester is developed to investigate the effects of the kinematics parameters on the electrical pitting formation mechanism for the common material of bearing by changing the supply voltage current and the oil film thickness. Result show that in the static condition, since the arc action causes the surface melting of two specimens, and the actions of coulomb force and electrostatic force cause the specimens to attract each other, the plateau can be observed on the surfaces of specimens. The plateau is like a bridge to connect two specimens. In this moment the plateau accumulates continuously and causes two specimens to produce the repulsive force. In the dynamic condition, the formation of pitting at the initial stage is quite similar to that in the static condition. Since the effect of sliding speed, the bridge is sheared and the friction force increases. Under the actions of joule heat and friction force, the surfaces of two specimens melt and scratch continuously. When the dynamic pitting occurs, the pitting width of square specimen, the normal force and the friction force increases with increasing supply voltage, supply current, and oil film thickness. When the interface power is larger, the melting phenomenon is more obvious, and the pitting width becomes larger. Because the surface melting and the actions of Coulomb force and electrostatic force cause the material accumulates continuously, the normal force and the friction force increase with increasing the interface power. To investigate all effects of experimental parameters on the pitting width, the empirical formula for the pitting width is established in terms of supply voltage, supply current, and oil film thickness. This formula can be used to predict oil film thickness or the size of pitting width on the bearing surface for diagnosing the lubricant condition of bearing.

A novel variation of Rutherford Backscattering Spectrometry (RBS) has been utilized to measure a high voltage collected on an aluminum target by Direct Energy Conversion. The maximum high voltage on the target was measured to be 97.5 kV +/- 2 kV. The resistance of the circuit was then calculated based on the current driving different target voltages. The resistance was calculated to be 199.4GΩ +/- 5%. It was shown that by simply measuring the neutral particles’ energy spectra, the voltage on the target and resistance of the circuit can be found with certainty. The experimental data agree well with previous work and with the scattering theory developed. Thus, the capability of RBS has been extended to measure high voltages generated by direct energy conversion; this is something that has not been done before.

The thesis is composed of two topics : a fully bidirectional mixed-voltage-tolerant I/O buffer using a clamping dynamic gate bias generator and a wide range fully bidirectional mixed-voltage-tolerant I/O buffer with a calibration function. The first topic, a mixed-voltage-tolerant I/O buffer implemented in 2P4M 0.35 £gm CMOS process, comprises a low-power bias circuit with clamping transistors in a feedback loop, a power supply level detector circuit, a voltage level converter circuit, a logic switch circuit, a dynamic driving detector circuit, and a clamping dynamic gate bias generator. The proposed design can transmit and receive digital signals with voltage levels of 5/3.3/1.8 V without any gate-oxide overstress and leakage current path in different voltage interface applications. The second topic, a 0.9 V to 5.0 V (0.9/1.2/1.8/2.5/3.3/5 V) mixed-voltage-tolerant I/O buffer carried out in 2P4M 0.35 £gm CMOS technology, contains a dynamic gate bias generator to provide appropri¬ate gate voltages for the output stage composed of stacked PMOS and stacked NMOS, an I/O buffer which can transmit the signal with a higher voltage level (VDDH), a floating N-well circuit to remove the body effect at the output PMOS, and a dynamic driving detector to balance the turn-on voltages for the pull-up PMOS and pull-down NMOS in the output stage. The duty cycle of the output signal of the proposed I/O buffer can then be equalized even if the output stage power supply is biased at a low voltage. In order to adapt to wide range input voltage applications, a logic calibration circuit is added in the input buffer.

Abstract The tendency to manufacture of semiconductor is to minimize the size of device. With the size was minimized, the number of transistor on the chip was maximized at the same time .However, when the drift region of Power-MOSFET is shorter will result in the Breakdown Voltage is lower, so this do not conform our purpose for application, and therefore we should look for some alternative method to enhance efficiency. One of these method of efficiency promotion is adopting channel strain. We adopt bending silicon substrate to obtain strain. By using this method, we successfully enhance drain current and mobility 12.1% and 4.1% individually. Furthermore, regarding the reliability study, we realize the hot-carrier effect influence under strain silicon. The longer the size(Lg & DL) of Power- MOSFET , the reliability is better. When device were bent under Bending R=40mm and Lg=0.8(m conditions, we can obtain the better reliability of device than flat chip.

Thesis (M.Eng.), Memorial University of Newfoundland, 2000. / Bibliography: leaves 115-118.

published_or_final_version / Electrical and Electronic Engineering / Master / Master of Philosophy

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