Extensive research has been done over the years and has contributed quite a lot to the development of 3CR12 stainless steel. Nevertheless, there is still much to be understood about the behaviour of this steel during its production. One of the problems that are occasionally encountered is the side bulging effect i.e. the unconstrained narrow faces of the strand plastically bulge due to ferrostatic pressure from the liquid core of the strand at high temperatures. In general, this problem is prevalent in ferritic stainless steels as they exhibit a weaker hot strength than austenitic stainless steels. Coupled with side bulging, there is also strand width variation at high temperatures i.e. when the steel is in the ferrite-austenite dual phase region. Both of these dimensional changes to the slab profile create some processing problems in subsequent hot rolling operations when unacceptable width variations are encountered. This work was, therefore, motivated by the requirement to quantify the role that the metallurgical behaviour of this steel plays with regard to the above width variation problem. The research work involved studies of the <font face="symbol">d</font>-ferrite to austenite phase change during continuous cooling (simulating cooling during continuous casting) and the establishment of CCT diagrams, the influence of chemical composition on the austenite start temperature and the hot ductility and hot strength visà-vis the side bulging effect. The casting conditions in the mould are crucial to ensure that the solidification shell is thick enough to withstand the ferrostatic pressure exerted on the unconstrained narrow sides of the strand as it exits from the mould. Therefore, part of the solution lies in the study of the optimisation of the cooling rate, mould flux properties, casting speed, mould taper angle and the chemical composition of this steel, among other factors. Additions of austenite formers, within the specification range of 3CR12, should be favourable for a stronger solidification shell since austenite exhibits superior hot strength to <font face="symbol">d</font>-ferrite. The good hot ductility observed in 3CR12 may also provide a leeway for increasing the secondary cooling rate in order to form a thicker solidification shell soon after emerging from the mould. This may reduce the side bulging effect. This can be achieved without a risk of transverse cracking if the cooling is adjusted carefully. As long as the <font face="symbol">d</font>-ferrite to austenite phase ratio keeps fluctuating due to variations in (i) the chemical composition within the specification range and (ii) the cooling rate in the dual phase region from cast to cast, the strand width variation effect will persist. This is simply because of the effect these have on the ferrite to austenite phase ratios through the differences between the lattice structures of these two phases. Ferrite being less dense than austenite, occupies more volume than austenite, thereby affecting the slab width. The remedy to this problem is to control within stricter chemical composition limits in order to reduce or completely avert this width variation effect. / Dissertation (MSc (Metallurgy))--University of Pretoria, 2006. / Materials Science and Metallurgical Engineering / unrestricted

A two-wire, low component count soil temperature sensor was developed. The sensor uses one wire for ground and the other wire is used for both power and communication. Pulse width modulation is used to send temperature measurements to the master, where the duty cycle is proportional to the temperature. The sensor parasitically powers itself from the bidirectional data line. In order to reduce the number of components necessary, a microcontroller with an internal temperature sensor is used. Finally, the sensor can receive data from the master on the bidirectional communication line, which is used for calibrating the sensor.

abstract: A Single Event Transient (SET) is a transient voltage pulse induced by an ionizing radiation particle striking a combinational logic node in a circuit. The probability of a storage element capturing the transient pulse depends on the width of the pulse. Measuring the rate of occurrence and the distribution of SET pulse widths is essential to understand the likelihood of soft errors and to develop cost-effective mitigation schemes. Existing research measures the pulse width of SETs in bulk Complementary Metal-Oxide-Semiconductor (CMOS) and Silicon On Insulator (SOI) technologies, but not on Fin Field-Effect Transistors (FinFETs). This thesis focuses on developing a test structure on the FinFET process to generate, propagate, and separate SETs and build a time-to-digital converter to measure the pulse width of SET. The proposed SET test structure statistically separates SETs generated at NMOS and PMOS based on the difference in restoring current. It consists of N-collection devices to collect events at NMOS and P-collection devices to collect events at PMOS. The events that occur in PMOS of the N-collection device and NMOS of the P-collection device are false events. The logic gates of the collection devices are skewed to perform pulse expansion so that a minimally sustained SET propagates without getting suppressed by the contamination delay. A symmetric tree structure with an S-R latch event detector localizes the location of the SET. The Cartesian coordinates-based pulse injection structure injects external pulses at specific nodes to perform instrumentation and calibrate the measurement. A thermometer-encoded chain (vernier chain) with mismatched delay paths measures the width of the SET. For low Linear Energy Transfer (LET) tests, the false events are entirely masked and do not propagate since the amount of charge that has to be deposited for successful event propagation is significantly high. In the case of high LET tests, the actual events and false events propagate, but they can be separated based on the SET location and the width of the output event. The vernier chain has a high measurement resolution of ~3.5ps, which aids in separating the events. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2020

No description available.

This thesis deals with design of devices for control and regulation of LEDs. The document summarizes basic information about light, its origin and variety. This work discusses the effects of light on humans. There are also discussed the possibilities of lighting control with LEDs. The work includes a diagram that describes a device for controlling and controlling light for daylight and night light.

This thesis deals with the monitoring of buildings disorders caused by surrounding con-struction activity. The first section describes the methods of monitoring failures, from the detailed inspection to the result evaluation, there is also given an overview of measuring instruments. The second part describes the methodology of passports implementation and contains an example of the object repassport that was violated by tunneling. There is a comparison of passport and repassport. The third largest section describes a practical ex-ample of monitoring object cracks around which the building activity took place. There is a documentation of failures, a description of the measuring spots choise, installation of the bases, monitoring, processing of results and conclusion.

Les unités à taille réduite font partie des méthodes proposées pour la réduction de la consommation d’énergie. Cependant, la plupart de ces unités sont évaluées séparément,c’est-à-dire elles ne sont pas évaluées dans une application complète. Dans cette thèse, des unités à taille réduite pour le calcul et pour l’accès à la mémoire de données, configurables au moment de l’exécution, sont intégrées dans un processeur RISC-V. La réduction d’énergie et la qualité de sortie des applications exécutées sur le processeur RISC-V étendu avec ces unités, sont évaluées. Les résultats indiquent que la consommation d’énergie peut être réduite jusqu’à 14% pour une erreur ≤0.1%. De plus, nous avons proposé un modèle d’énergie générique qui inclut à la fois des paramètres logiciels et architecturaux. Le modèle permet aux concepteurs logiciels et matériels d’avoir un aperçu rapide sur l’impact des optimisations effectuées sur le code source et/ou sur les unités de calcul. / Reduced width units are ones of the power reduction methods. However such units have been mostly evaluated separately, i.e. not evaluated in a complete applications. In this thesis, we extend the RISC-V processor with reduced width computation and memory units, in which only a number of most significant bits (MSBs), configurable at runtime is active. The energy reduction vs quality of output trade-offs of applications executed with the extended RISC-V are studied. The results indicate that the energy can be reduced by up to 14% for an error ≤ 0.1%. Moreover we propose a generic energy model that includes both software parameters and hardware architecture ones. It allows software and hardware designers to have an early insight into the effects of optimizations on software and/or units.

We study the extraction of nonlinear data models in high dimensional spaces with modified self-organizing maps. Our algorithm maps lower dimensional lattice into a high dimensional space without topology violations by tuning the neighborhood widths locally. The approach is based on a new principle exploiting the specific dynamical properties of the first order phase transition induced by the noise of the data. The performance of the algorithm is demonstrated for one- and two-dimensional principal manifolds and for sparse data sets.

Doctor Scientiae - DSc / Determining arch perimeter is of importance in both a clinical setting, where it is used to determine space requirements, as well as in an epidemiological setting where it is used to describe large populations. Physical measurement of arch perimeter is time consuming and may be prone to operator errors when done on study casts and even more so in a clinical situation. The use of a simple mathematical model to predict arch perimeter, using a few measurements that can be done easily and reliably, would be of great use to the practitioner.

In this thesis we will focus on a problem of length bounded cut, also known as L-bounded cut. We are going to show a combinatorial algorithm for finding a minimal L-bounded cut on graphs with bounded treewidth based on dynamic programming. Then we going to show that this algorithm can also be used for finding minimal L-bounded cut on plannar graphs. We are also going to look at problem of (dG(s, t) + 1)-bounded cut. This problem is known to be NP-hard for general graphs. But it is an open problem whether this problem is also NP-hard on plannar graphs with special vertices on the outer face. We will try to outline a way, which might lead to showing that this problem is solvable in a polynomial time.