Dans les modules de puissance à connexion filaire de type wire-bonding (WB), les forts courants commutés (jusqu’à 200A pour une puce de 10x10mm²) imposent de faibles résistances et inductances d’interconnexion pour réduire la chute de tension et les surtensions. Pour cette raison, les concepteurs multiplient les fils de bonding de grand diamètre (jusqu’à 500μm) en parallèle. De plus, quand la surface de puce le permet, les WB sont soudés à au moins deux endroits différents pour améliorer la distribution du courant. A la différence d’un assemblage standard de type WB, dans un module de puissance de type Direct-Lead-Bonding (DLB), la puce et la diode sont généralement brasées d’un côté, via la technique du flip-chip, sur le dissipateur intégré. L’autre face est brasée ou frittée directement sur une broche (ou clip) interne large pour former la maille électrique grâce à une brasure à base d'étain, d’argent et de cuivre (SAC ou Sn-Ag-Cu), très épaisse pour éviter le claquage broche-terminaison de puce. Par conséquent, le DLB peut offrir une surface de contact plus performante sur les plans électrique et thermique que le WB, réduisant ainsi la résistance de contact d’environ 50% selon la bibliographie (d’un facteur dix selon nos simulations électromagnétiques), améliorant la distribution du courant dans les puces et homogénéisant la température au sein du composant. De plus, l’inductance parasite interne peut être atténuée de 57% comparé au WB selon la littérature. Si l’on aborde la dimension sécuritaire, la tenue en surintensité ou I²T d’un module de puissance WB rempli de gel de silicone est faible et procure un effet fusible naturel bien qu’imparfait (mode de défaut circuit-ouvert). Les fils de bonding subissent un phénomène de soulèvement même si leur design n’a pas été pensé dans ce sens. En remplaçant le gel par de la résine époxy, ce comportement se dégrade pour donner un mode de défaut intermédiaire dû à la limitation en température de la résine. A l’inverse, le DLB devrait montrer un très fort I²T et donc, un mode de défaut se rapprochant du court-circuit. Ces travaux proposent une approche innovante sur le thème du design des topologies de conversion sécurisées à tolérance de panne : pourquoi ne pas construire une topologie autour du mode de défaillance intrinsèque d’un module de puissance, au lieu de mettre en place des moyens classiques pour le contrecarrer, i.e. essayer d'isoler systématiquement le défaut avec des fusibles ? Le module de puissance DLB était le candidat idéal pour mettre à l’œuvre notre philosophie. Dans un premier temps, nous avons cherché à comparer les modes de défaillance des deux technologies, WB et DLB, grâce à des essais destructifs d’énergies maîtrisés. Les résistances de défaut, énergies critiques et I²T ont été mesurées sur un banc dédié, de même que des analyses d'endommagements des zones de défaillance ont été réalisées au sein du CNES-THALES Lab de Toulouse par une méthode non intrusive de type Lock-In-Thermography (LIT). Il a été montré que la technologie DLB pouvait présenter une résistance de défaut dix fois plus faible que celle de la technologie WB à même surface de puce et à même énergie de destruction. La présence du clip permet aussi de réduire le gradient thermique dans la région du défaut et de moins contraindre thermiquement l'encapsulant par rapport à la technologie WB. La forte épaisseur du joint de brasure broche – puce garantit aussi une meilleure métallisation par refusion de la zone de perçage et ainsi une résistance de défaut plus faible. Dans un second temps, les modules détruits WB et DLB ont subi des essais d’endurance sur 5 semaines, afin d’éprouver la robustesse et la stabilité de leur résistance de défaut à faible et fort courants. Les résultats montrent clairement la supériorité de la technologie DLB. Par la suite, une campagne de caractérisation thermique (Rth/Zth) des deux technologies WB et DLB a été réalisée sur la base d'un banc développé à cet effet. / In wire-bonding (WB) power-modules, high current commutated by fast power chips (up to 200A on a 10x10mm² chip) implies low resistance and low stray inductance interconnections in order to reduce voltage drop and overvoltage. For this purpose, designers use numerous large-diameter bonding wires (up to 500μm) in parallel. Whenever the die surface is large enough (like IGBTs), bonding wires are soldered at least in two different spots to improve current distribution. Compared to conventional WB structure, inside Direct-Lead-Bonding (DLB) power-modules, chip and diode are generally soldered on one side, using flip-chip method, to the heat spreader. The other side is directly soldered or sintered to the large inner lead (or clip) to form the electrical loop with a thick standard SAC soldering (Sn-Ag-Cu) in order to avoid electrical breakdown between chip and clip. Therefore, DLB would provide a wider bonding area than WB design, reducing the emitter contact resistance by almost 50% in the literature (by a factor of 10 according to our simulation results), improving current uniformity in the chips and thus resulting in a uniform surface temperature distribution inside the device. Besides, DLB internal inductance could be reduced to 57% of wire-bonded modules according to literature. Considering safety aspects, the overcurrent capability of a gel-filled wire-bonding power module is low and provides a natural but imperfect wire-fuse-effect (as an open-failure mode). Lift-offs happen even if WB design is not optimized for it. Replacing the gel with an epoxy resin, this behaviour gets worse and an intermediate failure-mode is reached due to the epoxy temperature limitation. On the opposite, DLB should have a very high overcurrent capability characteristic and thus short-failure mode behaviour. This work offers a quite new approach in the field of fault-tolerant structure design: what if we use the faulty power module in a new way, instead of getting rid of it using classic methods to disconnect it, i.e. systematically isolating the power device using fuses? The DLB power module was the perfect candidate to experience our philosophy. In the first place, a comparison of both technologies has been performed through post-fault-behaviour characterisation using controlled energy failure tests. Post-fault resistances, critical energies and overcurrent capability have been measured on a dedicated test-bench, along with defect localization and analysis through micro-section thanks to the CNES-THALES Lab in Toulouse, using non-intrusive Lock-In Thermography (LIT) method. Failed DLB power-modules have showed post-fault resistances 10 times lower than wire-bonded power-modules with the same die size and the same destruction energy. The clip also reduces temperature gradient around the defect location and thus, releases the resin’s thermal constraints compared to WB technology. The very thick solder joint between clip and chip ensures a better metallic reforming and therefore a less resistive post-fault resistance. In the second place, faulty power modules under low and high destruction energy, both WB and DLB, have been tested during 5 weeks for durability and robustness. Results clearly show DLB supremacy. Then, a long campaign of thermal characterization of both designs (Rth/Zth) has been carried out thanks to another dedicated bench. We have proposed a new heating technique setting the die in its linear mode, which avoids using a high current power supply. We have modelled both designs using COMSOL Multiphysics in order for them to be simulated and compared in terms of thermal resistance and impedance, electrical resistance and inductance. The DLB thermal diffuser effect has been analysed. Thermal resistances are very similar (~0,13°C/W) meanwhile, surprisingly, WB is better than DLB in terms of thermal impedance with a maximum difference of 20% at 0.1s.

Submitted by Silvana Teresinha Dornelles Studzinski (sstudzinski) on 2016-08-04T14:39:04Z No. of bitstreams: 1 João Pedro Gonçalves Trevizan_.pdf: 2398963 bytes, checksum: 7bbf859367acdb155c3b917d8275c41d (MD5) / Made available in DSpace on 2016-08-04T14:39:04Z (GMT). No. of bitstreams: 1 João Pedro Gonçalves Trevizan_.pdf: 2398963 bytes, checksum: 7bbf859367acdb155c3b917d8275c41d (MD5) Previous issue date: 2016-06-15 / itt Chip - Instituto Tecnológico de Semicondutores da Unisinos / PADIS - Programa Federal de Apoio a Indústria de Semicondutores / Este estudo avalia uma proposta de substituição de fio de ouro por fio de cobre no processo de wire bonding em memórias DRAM DDR3 encapsuladas no Brasil. A viabilidade técnica da aplicação desta tecnologia para este componente foi testada na prática em uma empresa coreana, com a produção de amostras e verificação das características de qualidade das mesmas. Após otimização de parametros da primeira solda por DOE, foi possível obter resultados dentro das especificações do processo e semelhantes aos obtidos com o fio de ouro. Após a confirmação da viabilidade técnica, foi verificado a viabilidade econômica deste projeto, calculando o custo de implementação e estimando o tempo para retorno do investimento através dos métodos de payback simples e descontado. Devido à necessidade de aquisição de máquinas soldadoras de custo elevado, o payback descontado resultou em seis anos e onze meses, o que representa um risco alto considerando o dinamismo do mercado de semicondutores e a eminente substituição do encapsulamento BOC pela tecnologia de flip chip / This study evaluates the proposal of gold wire for copper wire replacement in the wire bonding process used in DRAM DDR3 memory packaging in Brazil. The technical feasibility of applying this technology to the component has been verifyed in practice on a Korean company, with the production of samples and the examination of quality characteristics, such as bond pull force and bond shear strenght, intermetallic compound and bonding pad structure. After parameters optimization of the first bond by DOE, it was possible to obtain results within process specifications and similar to those obtained with the gold wire. After confirming the technical feasibility, the economic viability of this project was verified by calculating the cost of implementation and the necessary time to recover the investment, through the simple and discounted payback methods. Because of the need of purchasing costly wire bonding machines, the discounted payback resulted in six years and eleven months, which represents a high risk investment, considering the semiconductor market dynamism and the imminent replacement of BOC package by flip chip technology.

This thesis demonstrates the feasibility of methods developed to increase the quality of the crescent bond together with the tail bond quality. Low pull force of the crescent bond limits the usage of insulated Au wire in microelectronics assembly. Premature break of the tail which results in the stoppage of the bonding machine is one of obstacles to overcome for Cu wire. The primary focus of this thesis is to understand the tail and crescent bonding process and then to propose methodologies to improve thermosonic wire bonding processes when Cu and insulated Au wires are used. Several series of experiments to investigate the crescent and tail bonding processes are performed on auto bonders. Cu and insulated Au wires with diameters of 25mm are bonded on the diepads of Ag leadframes. For simplicity, wire loops are oriented perpendicular to the ultrasonic direction. It was found that the crescent bond breaking force by pulling the wire loop (pull force) with insulated Au wire is about 80 % of that of bare Au wire. A modification of the crescent bonding process is made to increase the pull force with insulated Au wire. In the modified process, an insulation layer removing stage (cleaning stage) is inserted before the bonding stage. The cleaning stage consists of a scratching motion (shift) toward to the ball bond in combination with ultrasound. Bonds are then made on the fresh diepad with the insulation removed from the contact surface of the insulated Au wire. This process increases the pull force of the crescent bond up to 26% which makes it comparable to the results obtained with bare Au wire. An online tail breaking force measurement method is developed with a proximity sensor between wire clamp and horn. Detailed understanding of tail bond formation is achieved by studying tail bond imprints with scanning electron microscopy and energy dispersive x-ray analysis. Descriptions are given of the dependence of the tail breaking force on the bonding parameters, metallization variation, and cleanliness of the bond pad. Simultaneous optimization with pull force and tail breaking force can optimize the Cu wire bonding process both with high quality and robustness. It is recommended to first carry out conventional pull force optimization followed by a minimization of the bonding force parameter to the lowest value still fulfilling the pull force cpk requirement. The tail bond forms not only under the capillary chamfer, but also under the capillary hole. The tail breaking force includes both the interfacial bond breaking strength and the breaking strength of the thinned portion of the wire that will remain at the substrate as residue. Close investigations of the tail bond imprint with scanning electron microscopy indicate the presence of fractures of the substrate indicating substrate material being picked up by Cu wire tail. Pick up is found on Au and Cu wires, but the amount of pick up is much larger on Cu wire. The effect on the hardness of the subsequently formed Cu free air ball (FAB) as investigated with scanning electron microscopy and micro - hardness test shows that Cu FABs containing Au and Ag pick ups are softer than those without pick up. However, the hardness varies significantly more with Au pick up. The amount of Au pick up is estimated higher than 0.03 % of the subsequently formed FAB volume, exceeding typical impurity and dopant concentrations (0.01 %) added during manufacturing of the wire.

This thesis demonstrates the feasibility of methods developed to increase the quality of the crescent bond together with the tail bond quality. Low pull force of the crescent bond limits the usage of insulated Au wire in microelectronics assembly. Premature break of the tail which results in the stoppage of the bonding machine is one of obstacles to overcome for Cu wire. The primary focus of this thesis is to understand the tail and crescent bonding process and then to propose methodologies to improve thermosonic wire bonding processes when Cu and insulated Au wires are used. Several series of experiments to investigate the crescent and tail bonding processes are performed on auto bonders. Cu and insulated Au wires with diameters of 25mm are bonded on the diepads of Ag leadframes. For simplicity, wire loops are oriented perpendicular to the ultrasonic direction. It was found that the crescent bond breaking force by pulling the wire loop (pull force) with insulated Au wire is about 80 % of that of bare Au wire. A modification of the crescent bonding process is made to increase the pull force with insulated Au wire. In the modified process, an insulation layer removing stage (cleaning stage) is inserted before the bonding stage. The cleaning stage consists of a scratching motion (shift) toward to the ball bond in combination with ultrasound. Bonds are then made on the fresh diepad with the insulation removed from the contact surface of the insulated Au wire. This process increases the pull force of the crescent bond up to 26% which makes it comparable to the results obtained with bare Au wire. An online tail breaking force measurement method is developed with a proximity sensor between wire clamp and horn. Detailed understanding of tail bond formation is achieved by studying tail bond imprints with scanning electron microscopy and energy dispersive x-ray analysis. Descriptions are given of the dependence of the tail breaking force on the bonding parameters, metallization variation, and cleanliness of the bond pad. Simultaneous optimization with pull force and tail breaking force can optimize the Cu wire bonding process both with high quality and robustness. It is recommended to first carry out conventional pull force optimization followed by a minimization of the bonding force parameter to the lowest value still fulfilling the pull force cpk requirement. The tail bond forms not only under the capillary chamfer, but also under the capillary hole. The tail breaking force includes both the interfacial bond breaking strength and the breaking strength of the thinned portion of the wire that will remain at the substrate as residue. Close investigations of the tail bond imprint with scanning electron microscopy indicate the presence of fractures of the substrate indicating substrate material being picked up by Cu wire tail. Pick up is found on Au and Cu wires, but the amount of pick up is much larger on Cu wire. The effect on the hardness of the subsequently formed Cu free air ball (FAB) as investigated with scanning electron microscopy and micro - hardness test shows that Cu FABs containing Au and Ag pick ups are softer than those without pick up. However, the hardness varies significantly more with Au pick up. The amount of Au pick up is estimated higher than 0.03 % of the subsequently formed FAB volume, exceeding typical impurity and dopant concentrations (0.01 %) added during manufacturing of the wire.

As the IC assembly technology fast developing in the modern electrical industries. Demand of high performance electric product is glowing up day by day. New generation of the hybrid IC assembly package has become the major role recently. In order to prevent the package defects occurring in end customer sites, in this paper we try to improve the IC assembly method by using a totally different process to fix the passive component on a BGA substrate. We found that the passive component can be proceeded the current gold wire bonding process. In case of the Hybrid BGA with the current passive component attaching process, we can find the thermal effect during the surface mount process. Since the solder can be melt every time during each heating process. Therefore, we plan to improve it without solder attachment. The new improvement is to fix the passive component by a non-conductive thermal cure glue. The glue can be done in one time cure, thus the further process would not influence the quality of passive component. However in the evaluation experiment, the component coated by Gold is the best choice, but we intend to just put it in a comparison model because of the cost consideration. Both works on passive component coated by Gold and Solder were proved. The customer support for the further study on the real products is suggested.

Wire Bonder and Molding are the most costive equipments in the investment of IC packaging; and the packaging quality, cost and delivery are concerned most in the assembly processes. An inappropriate process scheduling may result in the wastes of resources and assembly bottleneck. Manager must allocate the resources appropriately to adapt the changeable products and production lines. We would introduce several heuristic search methods, especially the Tabu search. Tabu search is one of the most popular methods of heuristic search. We also use Tabu list to record several latest moves and avoid to the duplication of the paths or loops. It starts from an initial solution and keep moving the solution to the best neighborhood without stock by Tabu. The iterations would be repeated until the terminating condition is reached. At last of the report, an example will be designed to approach the best wire bonding and molding scheduling by Tabu search; and verify the output volume is more than those with FIFO in the same period of production time. Tabu search will be then confirmed to be effective for flexible flow shop.

Wire bonding is the process of creating interconnects between the circuitry on a microchip and PCB boards or substrates so that the microchip can interact with the outside world. The materials and techniques used in this bonding process can cause a wide variation in bond quality, so wire bond reliability testing is very important in determining the quality and longevity of wire bonds. Due to the fact that microchips are encased in protective resins after bonding and their substrates attached to the larger device as a whole, once any single wire bond fails then it could jeapordize the entire device as the wire bonds cannot be individually replaced or fixed. Current methods of reliability testing are lengthy and often destroy the entire sample in the process of evaluation, so the availability of novel non-destructive, real-time monitoring methods as well as accelerated aging could reduce costs and provide realistically timed tests of novel wire bond materials which do not form Intermetallic compounds (IMCs) as rapidly as Au wire on Al substrates. In this thesis, five new chip designs for use in wire bond reliability testing are reported, focusing on the first joint made in a wire bond, called the ball bond. These chips are scaled either to test up to 55 test bonds simultaneously or just one at a time, introducing different requirements for microchip infrastructure capabilities, such as on-chip sensing/data bus, multiplexer, and switches able to operate under High Temperature Storage (HTS) which ranges from temperatures of 150-220 ??C. There are different heating requirements for each of these microchips, needing to be heated externally or containing on-chip microheaters to heat only the ball bond under test, and not the rest of the microchip or surrounding I/O pads. Of the five chip designs, sample chips were produced by an external company. Experimental studies were then carried out with two of these chip designs. They were specifically made to test novel methods of determining ball bond reliability using in-situ, non-destructive sensing, in real-time, while the ball bond undergoes thermal aging. Pad resistance as an analysis tool for ball bond reliability is proposed in this thesis as a new way of evaluating ball bond quality and allows for the testing of electrical connection without the need for specialized measurement probes or difficult bonding processes that contact resistance measurements require. Results are reported for pad resistance measurements of a ball bond under very high temperature storage (VHTS) at 250 ??C, a temperature exceeding typical HTS ranges to accelerate aging. Pad resistance measurements are taken using the four-wire measurement method from each corner of the bond pad, while reversing current direction every measurement to remove thermo-electric effects, and then calculating the average square resistance of the pad from this value. The test ball bond is aged using a novel on-chip microheater which is a N+ doped Si resistive heater located directly underneath the bond pad, and can achieve temperatures up to 300 ??C while not aging any of the I/O pads surrounding it, which are located ~180 ??m away. A 50 ??? resistor is placed 60 ??m away from the heater to monitor the temperature. The use of a microheater allows the aging of novel wire types at temperatures much higher than those permitted for microchip operation while thermally isolating the test bond from the sensing and power bonds, which do not need to be aged. Higher temperatures allow the aging process to be sped up considerably. The microheater is programmatically cycled between 250 ??C (for 45 min) and 25 ??C (for 15 min) for up to 200 h or until the pad resistance measurements fail due breakdown of the bonding pad. Intermetallic compounds forming between the ball bond and the pad first become visible after a few hours, and then the pad becomes almost completely consumed after a day. The pad resistance is measured every few seconds while the sample is at room temperature, and the increase in pad resistance agrees with the fact that Au/Al IMC products are known to have much higher resistance than both pure Au or Al. Also discussed are some aging results of Au wires and Pd coated Cu (PCC) wires bonded to Al bonding pads and aged at a temperature of 200 ??C in an oven for 670 h. The oven aged Au ball bonds also saw IMC formation on the surface of the bonding pad, much like the microheater tests. The PCC ball bonds became heavily oxidized due to lack of Pd on the surface of the ball, the wire portions did not oxidize much. In conclusion, the new structures have been demonstrated to age ball bonds faster than with conventional methods while obtaining non-destructive data. Specifically, the new microheater ages a test bond at an accelerated rate without having an observable effect on the I/O connections used to monitor the test bond. Pad resistance measurements correlate to the aging of the test bond and ensure the electrical integrity of the joint is checked.

This work deals with a theoretical analysis of contacting semiconductor chips using wire-bonding method. There are mentioned basic types of chips packages and their contacts. In the thesis is also described software Ansys. The number of the mechanical stress and deformation simulation within micro-wire during thermocompress process were made.

This work deals with silicon chip interconnection with a view to high current up to 10A. A wire bonding method is used for interconnection. The first part of investigation is focused on the modeling and simulation by the help of program ANSYS. Thermo mechanical stressing and current density is important parts of this research. Stress and current density distribution are results of the first part. The experimental part describes transition resistance, electro migration and thermal process in the connection of wire and chip pad. A controlled current source (0 – 10A) is used for measurement. The current source makes it possible to 4-point method measurement with sampling rate 1,5MHz.

Through Silicon Vias (TSVs) are vertical interconnections providing the shortest possible signal paths between vertically stacked chips in 3D packaging. In this thesis, TSVs are fabricated and two novel approaches for the metal filling of TSVs are investigated. A wire bonder is utilized to apply TSV core material in the form of gold stud bumps. The metal filling approaches are carried out by 1) squeezing stud bumps down the TSV holes by utilizing a wafer bonder and 2) stacking stud bumps on the outer periphery of the TSV holes and thereby forcing the material further down. Both approaches have successfully filled TSV holes of varying depths and no voids have been observed. The squeezing approach reaches measured depths of up to 52.9 μm and the stacking approach reaches depths of up to 100 μm.