The CubeSat standard sprang from the desire to create a satellite standard that would open the doors for universities and other lower budget research institutions by making it more feasible to get their work into space. Since then, many other institutions and industries have been adopting variations on the standard for their own use. As more people are seeking out to use the CubeSat standard as their main bus, the standards and practices of the community have grown and expanded and with this growth, new challenges have been created. One such challenge is the bandwidth limitation in the RF-downlink. When carrying payloads requiring what might seem to be a relatively small (science data) bandwidth requirement (on the order of thousands of bps), the RF-link to ground is overloaded. Many approaches in the past have been put forth to help alleviate this issue, unfortunately, none have been fully adopted. This paper presents a solution that takes advantage of new technology yet to be fully exploited in space applications. The key to the solution lies in removing the bandwidth requirements by enabling onboard post-data processing and compression. In order to achieve the high computational needs, while minimizing power consumption, a Xilinx Zynq-7000 SoC is used, creating a highly-programmable, open integration device. This report outlines the design, fabrication and testing of this solution. The completion of the Zynq Processing System CubeSat Science Instrument Interface Electronics Board (or ZPS-Board), ultimately demonstrates the feasibility of this solution. Additionally, this research is funded by NASA’s JPL, with secondary motives for the creating of a space application Zynq-7000 SoC based product. Upon successful completion of the ZPS-Board, the product creates a platform for JPL to perform environmental testing in order to study the effects and performance characteristics of the Zynq in space applications.

The goal of this thesis is how to implement the two different types of the electric alternate motors in ZYNQ-7000 device for MIL real-time simulation purposes. The chosen types of motors are BLDC motor and AC induction motor. Mathematics models of these motor, the necessary changes for implementation purposes and the way how the models were implemented in ZYNQ-7000 device are described in this work. Three different experimental MIL simulation, using these motors ae described at the end of this thesis.

I dagens samhälle finns inbyggda system i allt från vattenkokare till rymdraketer. För att möta användarnas ständigt ökande krav på prestanda och funktionalitet måste hårdvaran i dessa system utnyttjas optimalt. Detta kan göras genom att konstruera hårdvara specifikt för den aktuella uppgiften eller att använda en mer generell hårdvara, där istället mjukvaran är anpassningsbar. I många fall kan det vara lämpligt, och i vissa fall även nödvändigt, att blanda dessa metoder för att lösa en given uppgift. En kraftfull processor kan exempelvis kompletteras med en accelerator uppbyggd av specifik hårdvara. Delar av lösningen kan genomföras snabbare i dessa acceleratorer vilket leder till ett bättre system. Problemet med denna lösningsmodell är dock att förbindelsen mellan processorn och acceleratorn ofta bildar en flaskhals för data som ska bearbetas. En metod för att minimera denna falskhals är att utveckla både programmerbar logik (FPGA, Field-Programmable Gate Array) och en processor på samma chip. Denna täta integration gör det möjligt att både förenkla och snabba upp kommunikationen mellan FPGA och processor. Xilinx har utvecklat ett sådant system, Zynq-7000, uppbyggd av en dubbelkärning ARM-processor och en kraftfull FPGA. Denna rapport beskriver det arbete som har utförts under detta examensarbete. Syftet med examensarbetet var att undersöka hur en specifik produktprototyp kan implementeras i Zynq-7000. Fokus för arbetet var att undersöka hur den interna kommunikationen bör genomföras och därigenom även hur lösningen bör partitioneras mellan mjukvara och hårdvara. Den tänkta produkten var ett system för bildigenkänning av frukter eller grönsaker för användning i en livsmedelsbutik. Under arbetet har utvecklingskortet ZedBoard, baserat på Zynq-7000, använts som målplattform. / In today's society there are embedded systems in almost everything from toasters to space rockets. In order to meet users’ ever-increasing demands for performance and functionality, the hardware of these systems must be utilized optimally. This can be done by designing hardware specifically for the task, or to use a more general hardware running customizable software. In many cases it may be suitable, and in some cases even necessary, to mix these methods to solve a given task. For example, a powerful processor could be complemented with special designed hardware, called an accelerator, to solve parts of the problem faster. The overall system performance can thus be increased by the use of the accelerators. One problem with this solution is that the connection between the processor and the accelerator may form a bottleneck. One way to reduce the effects of this bottleneck is to tightly integrate programmable logic (FPGA, Field Programmable Gate Array) and a processor on the same chip. This tight integration makes it possible to simplify and speed up the communication between the two units. For example, image processing could be accelerated in the FPGA and the result could then be used in some software application in the processor. This report describes how the work was carried out during this thesis. The main goal of the thesis was to study how a specific product prototype could be implemented using a Zynq-7000 based development board. The focus of this work was to study how the internal communication should be implemented, and there by how the solution should be partitioned between the software and hardware in Zynq-7000. The intended product was a system for image recognition of fruits or vegetables for use in a grocery store. During the work we used a Zynq-7000 based development board called ZedBoard to try our implementations.

<div>In autonomous driving, medical diagnosis, unmanned vehicles and many other new technologies, the neural network and computer vision has become extremely popular and influential. In particular, for classifying objects, convolutional neural networks (CNN) is very efficient and accurate. One version is the Region-based CNN (RCNN). This is our selected network design for a new implementation in an FPGA.</div><div><br></div><div>This network identies stop signs in an image. We successfully designed and trained an RCNN network in MATLAB and implemented it in the hardware to use in an embedded real-world application. The hardware implementation has been achieved with maximum FPGA utilization of 220 18k_BRAMS, 92 DSP48Es, 8156 FFS, 11010 LUTs with an on-chip power consumption of 2.235 Watts. The execution speed in FPGA is 0.31 ms vs. the MATLAB execution of 153 ms (on computer) and 46 ms (on GPU).</div>

Among many which are placed on modern embedded systems is also the need of storing multiple system boot image versions and the ability to select from them upon boot time, depending on a function which they provide. This thesis describes the development of a system update application for Xilinx Zynq-7000 devices. The application includes a simple embedded HTTP server for a remote file transfer. A client is allowed to upload the boot image file with the system update from either command line application or using the web page developed for this purpose.

Edge detection is one of the most important application in image processing. Field-Programmable Gate Arrays (FPGAs) have become popular computing platforms for signal and image processing. The Zynq-7000 System on Chip (SOC) is a dual-processor platform with shared memory. The thesis describes a novel and fast implementation of Sobel edge detection using the Zynq-7000 SoC. Our implementation is a combination of software and hardware using the Vivado HLS and Zynq (SoC). As a result our implementation is fast. We make a comparison with other conventional edge detection techniques and show that the speed of operation of this design is much faster.

In this exam project the investigation has been done to determine, which profits that can be made by switching an internal bus between two chips, one FPGA and a processor, to an internal bus implemented on only one chip, System on Chip. The work is based on measurements made in real time in Xilinx’s development tools on different buses, AXI4 and AXI4-Light connected to AXI3. The port that is used is FPGA’s own GP-port. Besides measuring the time of transactions also physical aspects have been investigated in this project: space, costs and time. Based on those criteria a comparison to the original construction was made to determine which benefits that can be achieved. The work has shown a number of results that are in comparison with the original construction. The System on Chip has turned out to be a better solution in most cases. When using the AXI4-Light-bus the benefits were not as obvious. Cosmic radiation, temperature or humidity are beyond the scope of this investigation. In the work the hypothetic deductive method has been used to prove that the System on Chip is faster than the original design. In this method three statements must be set up against each other; one statement that ought to be true, one statement that is a contradiction and a conclusion of what is proved. The pre-study pointed out that the System on Chip is a faster solution than the original construction. The method is useful since it proves that the pre-study is comparable to the measured results. / I detta examensarbete har undersökningar gjorts för att fastställa vilka vinster som går att göra genom att byta en internbuss mellan två chip, en FPGA och en processor, mot en intern buss implementerat på ett enda chip, System on Chip. Arbetet bygger på mätningar gjorda i realtid i Xilinx utvecklingsverktyg på olika bussar, AXI4 och AXI4‑Lite som är kopplade internt mot AXI3. Den port som används är FPGAs egen GP‑port. Förutom att mäta överföringshastigheterna, har även fysiska aspekter som utrymme, kostnader och utvecklingstid undersökts. Utifrån dessa kriterier har en jämförelse gjorts med den befintliga konstruktionen för att fastställa vilka vinster som går att uppnå. Arbetet har resulterat i ett antal resultat som är ställda mot de förutsättningar som fanns i den ursprungliga lösningen. I de flesta fall visar resultatet att ett System on Chip är en bättre lösning. De fall som var tveksamma var vid viss typ av överföring med AXI4‑Lite bussen. I arbetet har inte undersökning av kosmisk strålning, temperatur eller luftfuktighet betraktas. I arbetet med att försöka att bevisa att ett System on Chip är snabbare än den ursprungliga uppsättningen har utvecklingsmetoden hypotetisk deduktiv använts. Denna metod bygger på att man från början sätter upp ett påstående, som man förutsätter är sant, följt av en konjunktion, som inte får inträffa, för att slutligen dra en slutsats, som konstaterar fakta. Eftersom fakta som lästes in i början av arbetet pekade på att ett System on Chip var en snabbare och billigare lösning kändes metoden användbar. Under arbetets gång har det visat sig vara en bra metod som också ger ett resultat där sannolikheten för att det är en snabbare lösning ökar. Däremot säger inte metoden att det är helt säkert att den i alla situationer är bättre, vilket kan ändras om man använder andra förutsättningar eller tar med andra aspekter.

More complex and intricate Computer Vision algorithms combined with higher resolution image streams put bigger and bigger demands on processing power. CPU clock frequencies are now pushing the limits of possible speeds, and have instead started growing in number of cores. Most Computer Vision algorithms' performance respond well to parallel solutions. Dividing the algorithm over 4-8 CPU cores can give a good speed-up, but using chips with Programmable Logic (PL) such as FPGA's can give even more. An interesting recent addition to the FPGA family is a System on Chip (SoC) that combines a CPU and an FPGA in one chip, such as the Zynq-7000 series from Xilinx. This tight integration between the Programmable Logic and Processing System (PS) opens up for designs where C programs can use the programmable logic to accelerate selected parts of the algorithm, while still behaving like a C program. On that subject, Xilinx has introduced a new High-Level Synthesis Tool (HLST) called Vivado HLS, which has the power to accelerate C code by synthesizing it to Hardware Description Language (HDL) code. This potentially bridges two otherwise very separate worlds; the ever popular OpenCV library and FPGAs. This thesis will focus on evaluating Vivado HLS from Xilinx primarily with image processing in mind for potential use on GIMME-2; a system with a Zynq-7020 SoC and two high resolution image sensors, tailored for stereo vision.

This project deals with computation of eigenvalues and eigenvectors of Hermitian positive-semidefinite complex square matrix of order 4. The target is an implementation of computation in language VHDL to field-programmable gate array of type Xilinx Zynq-7000. This master project deals with algorithms used for computation of eigenvalues and eigenvectors of positive-semidefinite symmetric real square and positive-semidefinite complex Hermitian matrix and the analysis of algorithms by AnalyzeAlgorithm program assembled for this purpose. The closing part of this project describes implementation of the computation into field-programmable gate array with use of IP core Xilinx® Floating-Point \linebreak Operator and SVAOptimalizer, SVAInterpreter and SVAToDSPCompiler programs.