This thesis presents a new architecture for the reliable implementation of the symmetric-key algorithm Advanced Encryption Standard (AES) in Field Programmable Gate Arrays (FPGAs). Since FPGAs are prone to soft errors caused by radiation, and AES is highly sensitive to errors, reliable architectures are of significant concern. Energetic particles hitting a device can flip bits in FPGA SRAM cells controlling all aspects of the implementation. Unlike previous research, heterogeneous error detection techniques based on properties of the circuit and functionality are used to provide adequate reliability at the lowest possible cost. The use of dual ported block memory for SubBytes, duplication for the control circuitry, and a new enhanced parity technique for MixColumns is proposed. Previous parity techniques cover single errors in datapath registers, however, soft errors can occur in the control circuitry as well as in SRAM cells forming the combinational logic and routing. In this research, propagation of single errors is investigated in the routed netlist. Weaknesses of the previous parity techniques are identified. Architectural redesign at the register-transfer level is introduced to resolve undetected single errors in both the routing and the combinational logic. Reliability of the AES implementation is not only a critical issue in large scale FPGA-based systems but also at both higher altitudes and in space applications where there are a larger number of energetic particles. Thus, this research is important for providing efficient soft error resistant design in many current and future secure applications.

The constant matrix multiplication is one of the key operations in many applications including digital signal processing, communication, and coding. In general, constant matrix multiplication can be expressed as bit-level Boolean functions. Then, common subexpression elimination (CSE) can be used to reduce the area cost of realizing these bit-level functions by finding the shared common factors among these bit-level equations. The proposed circuit generator performs logic reduction on the input Boolean functions and produces the simplified Verilog HDL codes as output. Then the simplified code is fed into Synopsys Design Compiler for further logic minimization and technology mapping to generate gate-level netlists. In this thesis, we present ten different CSE algorithms for logic reduction of the bit-level Boolean functions. The comparisons include both the architecture-level technology-independent results and the Synopsys synthesized technology-dependent results. According to the experiments, we observe that our CSE can effectively reduce the area cost. We also apply the CSE to the design of the Advanced Encryption Standard (AES) in cryptography.

In giant magnetoresistance (GMR) or tunneling magnetoresistance (TMR) materials, the transport properties rely on the related spin configurations, i.e., the parallel spin configuration in both magnetic layers is responsible for the lower resistivity state while the antiparallel spin configuration between them exhibit the higher resistivity state. However, the magnetic materials in realistic do not align completely in one direction; they exhibit magnetic domains to reduce the dipolar interaction instead. It is thus crucial to investigate in detailed about how the magnetic domain evolution influences the magnetoresistance in GMR or TMR materials. So, Photoemission Electron Microscopy (PEEM) and Kerr microscope are very good tools for us to study the magnetic domain in local area. The in-situ preparation Mn/Ag wedge/Fe(100) ultrathin films are measured by Auger electron spectroscopy (AES), low energy electron diffraction (LEED), medium energy electron diffraction (MEED), and photoemission electron microscope (PEEM) in an ultrahigh vacuum chamber. The preparation Ti/Fe/Ti/SiO2/Si(100) thin films are performed in an ultrahigh vacuum chamber and then are measured by Kerr Microscopy in air. By observing the evolution of magnetic domain, we can know more the detailed information on magnetism microscopically and the correlation between the magnetic properties and electric transport properties.

This thesis presents an analysis of the implementation feasibility of RAM authentication and encryption. Past research as used simulations to establish that it is possible to authenticate and encrypt the contents of RAM with reasonable performance penalties by using clever implementations of tree data structures over the contents of RAM. However, previous work has largely bypassed implementation issues such as power consumption and silicon area required to implement the proposed schemes, leaving implementation details unspecified. This thesis studies the implementation cost of AES-GCM hardware and software solutions for memory authentication and encryption and shows that software solutions are infeasible because they are too costly in terms of performance and power, whereas hardware solutions are more feasible. / text

The Advanced Encryption Standard is one of the most common encryption algorithms. It is highly resistant to mathematical and statistical attacks, however, this security is based on the assumption that an adversary cannot access the algorithm’s internal state during encryption or decryption. Power analysis is a type of side-channel analysis that exploit information leakage through the power consumption of physical realisations of cryptographic systems. Power analysis attacks capture intermediate results during AES execution, which combined with knowledge of the plaintext or the ciphertext can reveal key material. This thesis studies and compares simple power analysis, differential power analysis and template attacks using a cheap consumer oscilloscope against AES-128 implemented on an 8-bit microcontroller. Additionally, the shuffling and masking countermeasures are evaluated in terms of security and performance. The thesis also presents a practical approach to template building and device characterisation. The results show that attacking a naive implementation with differential power analysis requires little effort, both in preparation and computation time. Template attacks require the least amount of measurements but requires significant preparation. Simple power analysis by itself cannot break the key but proves helpful in simplifying the other attacks. It is found that shuffling significantly increases the number of traces required to break the key while masking forces the attacker to use higher-order techniques.

Στην παρούσα διπλωματική εργασία παρουσιάζεται η μελέτη των αλγορίθμων AES και Rijndael καθώς και η υλοποίησή τους με δύο διαϕορετικούς τρόπους, ένας χρησιμοποιώντας εξ’ ολοκλήρου την CPU και άλλος ένας χρησιμοποιώντας τις CPU/GPU με την χρήση της CUDA. Αρχικά, παρουσιάζεται η λογική της σχεδίασης των αλγορίθμων AES και Rijndael καθώς και τα πλεονέκτηματα και μειονεκτήματά τους. Στη συνέχεια, γίνεται μία ανάλυση των διαϕορετικών τρόπων υλοποίησης των αλγορίθμων και παρουσιάζεται ο τρόπος υλοποίησης που επιλέχθηκε, ο electronic codebook, και o λόγος που έγινε αυτή η επιλογή. Τέλος, παρουσιάζονται τα αποτελέσματα και οι πειραματικές μετρήσεις καθώς και τα συμπεράσματα που βγαίνουν αναλύοντας τις γραϕικές παραστάσεις. / In this thesis, algorithms AES and Rijndael are studied and their implementation is presented in two different ways, one way using entirely the CPU and another way using CPU / GPU and CUDA. Initially, the logic behind algorithms AES and Rijndael is presented, as well as their advantages and disadvantages. Consequently, there is an analysis of the different implementations of the algorithms, as well as the reasons behind the selected implementation, the electronic codebook. Finally, the results and experimental measurements are presented and the conclusions according to the graphs' analysis.

This thesis presents a new architecture for the reliable implementation of the symmetric-key algorithm Advanced Encryption Standard (AES) in Field Programmable Gate Arrays (FPGAs). Since FPGAs are prone to soft errors caused by radiation, and AES is highly sensitive to errors, reliable architectures are of significant concern. Energetic particles hitting a device can flip bits in FPGA SRAM cells controlling all aspects of the implementation. Unlike previous research, heterogeneous error detection techniques based on properties of the circuit and functionality are used to provide adequate reliability at the lowest possible cost. The use of dual ported block memory for SubBytes, duplication for the control circuitry, and a new enhanced parity technique for MixColumns is proposed. Previous parity techniques cover single errors in datapath registers, however, soft errors can occur in the control circuitry as well as in SRAM cells forming the combinational logic and routing. In this research, propagation of single errors is investigated in the routed netlist. Weaknesses of the previous parity techniques are identified. Architectural redesign at the register-transfer level is introduced to resolve undetected single errors in both the routing and the combinational logic. Reliability of the AES implementation is not only a critical issue in large scale FPGA-based systems but also at both higher altitudes and in space applications where there are a larger number of energetic particles. Thus, this research is important for providing efficient soft error resistant design in many current and future secure applications.

Orientador: Maria Isabel Felisberti / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Quimica / Made available in DSpace on 2018-08-12T11:50:16Z (GMT). No. of bitstreams: 1 Faria_ElaineCristina_M.pdf: 2819560 bytes, checksum: 35692ba489585c42469cd45337f16702 (MD5) Previous issue date: 2008 / Resumo: Neste trabalho, foram preparadas blendas de poli(cloreto de vinila), PVC, com elastômero termoplástico poli[estireno-g(etileno-co-propileno-co-dieno)-g-acrilonitrila), AES. O AES é uma mistura complexa de poli(estireno-co-acrilonitrila), SAN, poli(etileno-co-propileno-co-dieno), EPDM e do copolímero de enxertia EPDM-g-SAN. As blendas com 10, 20 e 30% de AES foram obtidas em extrusora dupla-rosca cônica. As blendas PVC/AES são heterogêneas, apresentando uma fina dispersão da fase EPDM na matriz da blenda. Análise dinâmico-mecânica e calorimetria diferencial de varredura mostraram fortes indícios de que há um certo grau de miscibilidade da fase SAN do AES e o PVC. Mais especificamente, foram observadas duas transições vítreas para as blendas; a da fase EPDM, deslocada para temperaturas menores em relação à fase EPDM do AES; a da matriz, deslocada para temperaturas intermediárias entre as transições do do PVC e do SAN. Esta miscibilidade entre a fase SAN do AES e o PVC, que resultou em uma boa adesão entre a fase PVC e a fase EPDM da blenda, levando a uma melhora significativa nas propriedades de resistência ao impacto e alongamento do PVC. As blendas de 10, 20 e 30% de AES apresentaram um aumento de 240, 460 e 160% respectivamente, no alongamento do PVC e as blendas de 20 e 30% de AES apresentaram respectivamente um aumento da resistência ao impacto de 2000 e 2700% se comparadas ao PVC original. / Abstract: Abstract: In this work blends of polyvinyl chloride, PVC and the thermoplastic elastomer poly[acrylonitrile-g-(ethylene-co-propylene-co-diene)-g-styrene] were prepared. AES is a complex mixture of poly[stiren-co-acrylonitrile), SAN, and poly (ethylen-co-propylene-co-diene), EPDM and the graft copolymer EPDM-g-SAN. These blends were prepared ina twin-screw conic extruder in the following compositions: 10, 20 and 30% wt of AES. The blends are heteroneneos, presenting a thin phase dispersion of EPDM in the matrix. Dinamic-mechanical analysis (DMA) and Differential Electronic Calorimitry (DSC) showed miscibility between PVC and SAN phase of AES. Two glass transitions were observed for blends: one related to EPDM phase, shifted to lower temperatures in comparison to EPDM in the neat AES and another to matrix, intermediate to PVC and SAN glass transition temperatures. The miscibility between SAN phase and PVC, which promotes a good adhesion between PVC and EPDM significantly improved the impact resistance and elongation. The blends of 10, 20 and 30% of AES present an increase in elongation values in 240, 460 and 160% respectively and the blends of 20 and 30% of AES present an improvement of impact resistance of 2000 and 2700% respectively comparing to the original PVC / Mestrado / Físico-Química / Mestre em Química

The major challenges facing resource constraint wireless devices are error resilience, security and speed. Three joint schemes are presented in this research which could be broadly divided into error correction based and cipher based. The error correction based ciphers take advantage of the properties of LDPC codes and Nordstrom Robinson code. A cipher-based cryptosystem is also presented in this research. The complexity of this scheme is reduced compared to conventional schemes. The securities of the ciphers are analyzed against known-plaintext and chosen-plaintext attacks and are found to be secure. Randomization test was also conducted on these schemes and the results are presented. For the proof of concept, the schemes were implemented in software and hardware and these shows a reduction in hardware usage compared to conventional schemes. As a result, joint schemes for error correction and security provide security to the physical layer of wireless communication systems, a layer in the protocol stack where currently little or no security is implemented. In this physical layer security approach, the properties of powerful error correcting codes are exploited to deliver reliability to the intended parties, high security against eavesdroppers and efficiency in communication system. The notion of a highly secure and reliable physical layer has the potential to significantly change how communication system designers and users think of the physical layer since the error control codes employed in this work will have the dual roles of both reliability and security.

Information is an intelligent data through which knowledgeable and usable things can be convicted or interpreted in a proper manner. With the advancement of technology, transmission of information over the network has come a trend. This information must be transmitted securely over the network. Data security was not a problem if a secure channel was provided for single transmission. It is a necessity to convert the information into an unintelligible form for transmitting it over an unsecured channel. Encryption is a technique through which original information can be converted into unintelligible form. As time has elapsed, various encryption algorithms are employed so that information can be transmitted securely over an unsecured channel. Unless an intruder accesses the encrypted text, he / she cannot gain any information from that text. But as the new algorithms are designed, all the algorithms are challenged and their cryptanalysis is available. In the year 1998, Advanced Encryption Standards (A (S)) were proposed and later it was widely accepted as the most secure encryption algorithm that can be used to encrypt the information so that it can be transmitted securely and unsecured. fixed to a new scheme called Parallel AЕS, was an employee who takes four blocks of 16 bytes at a time to generate four blocks of 16 bytes of text thus providing diffusion of blocks at exchange. than all sequential AЕs. All the algorithms are challenged and their cryptanalysis is available. In the year 1998, To make A morS more fixed to a new scheme called Parallel AЕS, was an employee who took four blocks of 16 bytes at a time to generate four blocks of 16 bytes of text, thus providing diffusion of blocks at exchange. By doing this parallel A stoodS stood to be much firmer than sequential AЕS. Advanced Encryption Standards (AЕS) was proposed and later it was widely accepted as the most secure encryption algorithm that can be used to encrypt the information so that it can be transmitted securely over an unsecured channel. To make A morS more fixed to a new scheme called Parallel AЕS, was an employee who took four blocks of 16 bytes at a time to generate four blocks of 16 bytes of text, thus providing diffusion of blocks at exchange. By doing this parallel A stoodS stood to be much firmer than sequential AЕS. Advanced Encryption Standards (AЕS) was proposed and later it was widely accepted as the most secure encryption algorithm that can be used to encrypt the information so that it can be transmitted securely over an unsecured channel. To make A morS more fixed to a new scheme called Parallel AЕS, was an employee who took four blocks of 16 bytes at a time to generate four blocks of 16 bytes of text, thus providing diffusion of blocks at exchange. By doing this parallel A stoodS stood to be much firmer than sequential AЕS. was an employee who took four blocks of 16 bytes at a time to generate four blocks of 16 bytes of text, thus providing diffusion of blocks at exchange. By doing this parallel A stoodS stood to be much firmer than sequential AЕS. was an employee who took four blocks of 16 bytes at a time to generate four blocks of 16 bytes of text, thus providing diffusion of blocks at exchange. By doing this parallel A stoodS stood to be much firmer than sequential AЕS.