As CMOS processes size continues to shrink, a number of factors limit the ability of analog circuit performance to scale with the process. These issues include smaller transistor intrinsic gains and lower supply voltages. However, scaling continues to increase the speed and decrease the power of digital circuits. In this thesis, an active time-based integrator is proposed to replace amplifiers. The integrator, implemented using highly digital ring oscillators, seeks to take advantage of benefits offered by technology scaling while negating the issues of low gain and low supply voltages. The proposed integrator topology is used in a 20MHz 4th order continuous-time analog filter. Designed in a 90nm CMOS process, the time-based continuous-time filter achieves superior noise and linearity performance compared to state-of-the-art conventional active RC filters in simulations. / Graduation date: 2012 / Access restricted to the OSU Community at author's request from June 17, 2011 - June 17, 2012

A fully-differential base-band transimpedance low-pass filter is designed for use in a direct conversion wireless receiver. Existing base-band transimpedance amplifiers (TIA) often utilize single-pole filters which do not provide good stop-band rejection and may even allow the filter to saturate in the presence of large interferers near the edge of the pass-band. The designed filter is placed in parallel with an existing single-pole TIA filter and diverts stop-band current signals away from the existing filter, providing added rejection and safeguarding the filter from saturating. The presented filter has a bandwidth of 10 MHz, achieves 35 dB rejection at 50 MHz (25 dB in post-layout simulations), and can process interferers as large as 10 mA. The circuit is designed in Jazz 0.18 m CMOS technology, and it is shown, using macromodels, that the design is scalable to smaller, faster technologies.

Because of the huge bandwidth of Ultra-Wideband (UWB) systems, in-band narrowband interference may hinder receiver performance. In this dissertation, sources of potential narrowband interference that lie within the IEEE 802.15.3a UWB bandwidth are presented, and a solution is proposed. To combat interference in Multi-Band OFDM (MB-OFDM) UWB systems, an analog notch filter is designed to be included in the UWB receive chain. The architecture of the filter is based on feed-forward subtraction of the interference, and includes a Least Means Squared (LMS) tuning scheme to maximize attenuation. The filter uses the Fast Fourier Transform (FFT) result for interference detection and discrete center frequency tuning of the filter. It was fabricated in a 0.18 µm process, and experimental results are provided. This is the first study of potential in-band interference sources for UWB. The proposed filter offers a practical means for ensuring reliable UWB communication in the presense of such interference. The Operational Transconductance Amplifier (OTA) is the predominant building block in the design of the notch filter. In many cases, OTAs must handle input signals with large common mode swings. A new scheme for achieving rail-to-rail input to an OTA is introduced. Constant gm is obtained by using tunable level shifters and a single differential pair. Feedback circuitry controls the level shifters in a manner that fixes the common mode input of the differential pair, resulting in consistent and stable operation for rail-to-rail inputs. As the new technique avoids using complimentary input differential pairs, this method overcomes problems such as Common Mode Rejection Ratio (CMRR) and Gain Bandwidth (GBW) product degradation that exist in many other designs. The circuit was fabricated in a 0.5µm process. The resulting differential pair had a constant transconductance that varied by only ±0.35% for rail-to-rail input common mode levels. The input common mode range extended well past the supply levels of ±1.5V, resulting in only ±1% fluctuation in gm for input common modes from -2V to 2V.

In Multi-Standard receivers, multiple radios co-exist in close proximity. A desired signal can be accompanied by significantly stronger out-of band interferers or blockers, which can severely degrade a receiver's sensitivity through gain compression of the blocks in the receiver chain. This work presents a new Transimpedance Amplifier (TIA) low-pass filter architecture which seeks to solve the out-of-band blocker problem of the existing architectures. A higher order filtering is embedded within the TIA in the form of an active feedback to provide more attenuation to out-of-band blockers. The active feedback circuitry feeds back an equivalent amount of current to the input node to cancel out incoming out-of-band blockers while maintaining an acceptable voltage swing at the output of the TIA. The proposed TIA filter has a channel bandwidth of 20MHz, and can processes interferers of +/- 10mA fully differential without saturating the opamps. The maximum single ended voltage swing at all the nodes is +/- 200mV. All the circuits were designed in IBM 180nm CMOS process with a supply voltage of 1.8V.

No description available.

An 80 MHz bandpass filter with a tunable quality factor of 16∼44 using an improved transconductor circuit is presented. A noise optimized biquad structure for high-Q, high- frequency bandpass filter is proposed. The quality factor of the filter is tuned using a new quality factor locked loop algorithm. It was shown that a second-order quality factor locked loop is necessary and sufficient to tune the quality factor of a bandpass filter with zero steady state error. The accuracy, mismatch, and sensitivty analysis of the new tuning scheme was performed and analyzed. Based on the proposed noise optimized filter structure and new quality factor tuning scheme, a biquad filter was designed and fabricated in 0.25 μm BiCMOS process. The measured results show that the biquad filter achieves a SNR of 45 dB at IMD of 40 dB. The P-1dB compression point and IIP3 of the filter are -10 dBm and -2.68 dBm, respectively. The proposed biquad filter and quality factor tuning scheme consumes 58mW and 13 mW of power at 3.3 V supply.

Thesis describes the design of the blocks of fractional-order filters approximation using a filter of higher order integer. Active filters of third-order are use to create filter of 1+alfa -order, where alfa is between zero to one. One of the filters is practically implemented and measured.

Thesis describes the design of the blocks of fractional-order filters approximation using a filter of higher order integer. Active filters of third-order are use to create filter of 1+alfa -order, where alfa is between zero to one. One of the filters is practically implemented and measured.

The state-variable analog filter topologies are described. Using the transfer function theory and operational configurations suitable for integration and derivation, a new universal filter topology are proposed. The circuit has been implemented in CMOS technology by using six operational amplifiers, eight analog switches and five programming resistor array. Tunable corner frequencies, quality factors and gain are realized. Using the serial peripheral interface or digital memory can be realized this real-time digitally programmable first- and second-order analog filter with the tunable parameters.

This work analyzes tuning capabilities of different fully integrated active filter topologies. Work only deals with continuous time active filters. Topologies described in this work differ in type of active element and in method of frequency tuning. Techniques of tunning are proved on second order low pass filter. Filter topologies are compared from tunning capabilities and from point of total harmonic distortion. The main building block of all filters is integrator.