Societal concerns on combustion-based fuel consumption are ever-increasing. With respect to internal combustion engines, this translates to a need to increase brake fuel conversion efficiency (BFCE). Diesel engines are a relatively efficient internal combustion engine to consider for numerous applications, but associated actions to mitigate certain exhaust emissions have generally deteriorated engine efficiency. Conventionally, diesel engine emission control has centered on in-cylinder techniques. Although these continue to hold promise, the industry trend is presently favoring the use of after-treatment devices which create new opportunities to improve the diesel engine's brake fuel conversion efficiency. This study focuses on injection timing effects on the combustion processes, engine efficiency, and the engine system's responses. The engine in the study is a medium duty diesel engine (capable of meeting US EPA Tier III off road emission standards) equipped with common rail direct fuel injection, variable geometry turbo charging, and interfaced with a custom built engine controller. The study found that injection timing greatly affected BFCE by changing the combustion phasing. BFCE would increase up to a maximum then begin to decrease as phasing became less favorable. Combustion phasing would change from being mostly mixing controlled combustion to premixed combustion as injection timing would advance allowing more time for fuel to mix during the ignition delay. Combustion phasing, in turn, would influence many other engine parameters. As injection timing is advanced, in-cylinder temperatures and pressures amplify, and intake and exhaust manifold pressures deteriorate. Rate of heat release and rate of heat transfer increase when injection timing is advanced. Turbocharger speed falls with the advancing injection timing. Torque, however, rose to a maximum then fell off again even though engine speed and fueling rate were held constant between different injection timings. Interestingly, the coefficient of heat transfer changes from a two peak curve to a smooth one peak curve as the injection timing is advanced further. The major conclusion of the study is that injection advance both positively and negatively influences the diesel engine's response which contributes to the brake fuel conversion efficiency.

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The research was focus on exploring the growth strategy of small and medium business in Taiwan. We are interested in finding the orbit and the logic of Taiwan¡¦ small and medium business, which are growing rapidly and becoming global business recently. However, how to explicit the competitive advantage of business growth is a complicated and tacit task. The methodology of the research applied the grounded theory to do the qualitative analysis. After sampling from Taiwan passive component industry base on the strategic group, we will proceed the in-depth interview with the top management team of the businesses. The first-hand data and information from interview will be analysis, comparative, and coding repeatedly and iteratively. Gradually, the category and abstract concept will be emergent from the outcome of coding. The theory will be constructed from the relation of the concepts until the saturation it reached. The research founded that to catch the "strategic timing fit" was the orbit and the logic of Taiwan¡¦ passive component industry. There were three timing in the rapidly changing and creative environment: a) timing of technological paradigm transition; b) timing of production transition; c) timing of entrance and existence of competitors. The leaders of the firms in the case showed that they built the strategic capabilities and resources within the organization to meet the "strategic timing fit", which was the key factor of rapid growth in the past decade.

In1987, the Government released the law about restricting people to cotact between Taiwan and China, and the trade between Taiwan and China became more and more important. With the trend of economic community in globe and the industrial environment in Taiwan changed, the Multinational Enterprises (MNEs) should think about them how to keep advantages in global competition. Internationalization is the best choice that can help Taiwanese enterprises promote their competitive position in the world. China is a developing market and a lot advantages, such as rich resources and cheaper labors. Above all, China has become the major location of Taiwanese firm¡¦s foreign direct investment. Compared with the process of MNEs located in North America/European Unit (developed countries, DC), the international process of Taiwan¡¦s MNEs is very different with in other countries. This is interested topic to investigate the entry strategies of Taiwanese firm¡¦s FDI in China. Focused on China, this thesis try to find out the model of entry mode and entry timing. The two basic types of entry mode are wholly owned subsidiary (WOS) and joint venture (JV). This study also defined the FDI timing of 1993 is the intermediary to differentiate early entrant from latter entrant. The study collects 48 effective cases from electronics and non-electronics industries. The analytical technique used in this research includes descriptive statistics, factor analysis, cluster analysis, bivariate correlations, Multivariate Analysis Covariate of Variance (MANCOVA) and logistic regression. The study finds that the strategic roles of the MNEs have significant influences on the choice of entry mode. With different strategic motivations, the type of entry mode and the timing of entry are also difference. The relationship between entry mode and entry timing is not significant. In the view of global logistic management, Taiwan¡¦s MNEs will be an early entrant in China.

Synchronization is a challenging but very important task in communications. In digital communication systems, a hierarchy of synchronization problems has to be considered: carrier synchronization, symbol timing synchronization and frame synchronization. For bandwidth efficiency and burst transmission reasons, the former two synchronization steps tend to favor non-data aided (NDA or blind) techniques, while in general, the last one is usually solved by inserting repetitively known bits or words into the data sequence, and is referred to as a data-aided (DA) approach. Over the last two decades, extensive research work has been carried out to design nondata-aided timing recovery and carrier synchronization algorithms. Despite their importance and spread use, most of the existing blind synchronization algorithms are derived in an ad-hoc manner without exploiting optimally the entire available statistical information. In most cases their performance is evaluated by computer simulations, rigorous and complete performance analysis has not been performed yet. It turns out that a theoretical oriented approach is indispensable for studying the limit or bound of algorithms and comparing different methods. The main goal of this dissertation is to develop several novel signal processing frameworks that enable to analyze and improve the performance of the existing timing recovery and carrier synchronization algorithms. As byproducts of this analysis, unified methods for designing new computationally and statistically efficient (i.e., minimum variance estimators) blind feedforward synchronizers are developed. Our work consists of three tightly coupled research directions. First, a general and unified framework is proposed to develop optimal nonlinear least-squares (NLS) carrier recovery scheme for burst transmissions. A family of blind constellation-dependent optimal "matched" NLS carrier estimators is proposed for synchronization of burst transmissions fully modulated by PSK and QAM-constellations in additive white Gaussian noise channels. Second, a cyclostationary statistics based framework is proposed for designing computationally and statistically efficient robust blind symbol timing recovery for time-selective flat-fading channels. Lastly, dealing with the problem of frame synchronization, a simple and efficient data-aided approach is proposed for jointly estimating the frame boundary, the frequency-selective channel and the carrier frequency offset.

Delay test in nano-scale VLSI circuits becomes more difficult with shrinking technology feature sizes and rising clock frequencies. In this dissertation, we study three challenging issues in delay test: fault modeling, variational delay evaluation and path selection under process variation. Previous research of fault modeling on resistive spot defects, such as resistive opens and bridges in the interconnect, and resistive shorts in devices, lacked an accurate fault model. As a result it was difficult to perform fault simulation and select the best vectors. Conventional methods to compute variational delay under process variation are either slow or inaccurate. On the problem of path selection under process variation, previous approaches either choose too many paths, or missed the path that is necessary to be tested. We present new solutions in this dissertation. A new fault model that clearly and comprehensively expresses the relationship between electrical behaviors and resistive spots is proposed. Then the effect of process variations on path delays is modeled with a linear function and a fast method to compute coefficients of the linear function is also derived. Finally, we present the new path pruning algorithms that efficiently prune unimportant paths for test, and as a result we select as few as possible paths for test while the fault coverage is satisfied. The experimental results show that the new solutions are efficient and accurate.

Former research on entry strategies are generally focused on finding the determining factors for MNCs' entry timing or entry mode. Albeit MNCs' ultimate reason of investing in foreign markets are gaining profits, number of papers discussing MNCs' strategies and the performance of their subsidiary are far away from representing its importance ¡V especially in the realm of service industries. Meanwhile, along with advanced technology and the trend of globalization, international trades are flourishing. Financial firms are as well in the bloom due to their job as being capital borrowers and lenders. In Taiwan, since the government allowed foreign banks to invest in 1964, foreign banks contributed much in breeding financial innovation and training professionals. Their performances are as well benchmarks for domestic banks. Combined with aforementioned backgrounds and motives, this thesis aims at discussing the relation between the resources and decisions of the foreign banks' parent firms and its Taiwan branches' performance in order to figure out the key factor affecting the performance of these banks' Taiwan branches. Thus, this study will serve foreign banks' Taiwan branches as samples and list resource condition variables of their parent banks according to OLI framework. The entry timing of these foreign banks is served as the strategy behavior variable. Via analyzing sample data before and after the Financial Holding Company Act and Merger and Acquisition of Financial Institutions Act with multiple regressions, this study intends to confirm the key factor affecting the performance of these banks' Taiwan branches. According to the results, the key factor would be entry timing. That is, regardless of the environmental challenges posed against these banks, the first mover advantage dominates in explaining the performance of these banks' Taiwan branches.

Baker and Wurgler (2002) proposed market timing theory and indicated the observed capital structures are the outcomes that managers timed the equity market and took advantages of timing when information asymmetry is low and stock price is high. But many scholars argue that Baker and Wurgler¡¦s timing proxy is noisy, this study attempts to use the concept of Huang and Ritter (2009) to test market timing effect on capital structure more directly by cost of equity. The cost of equity in this study is estimated by Fama and French three factors model with five-year rolling regression which is different from Huang and Ritter (2009). The empirical results show that publicly traded firms in Taiwan Stock Exchange from 1996 to 2007 tend to issue debt when the cost of equity is high and issue equity when the cost of equity is low which means the timing of financing behavior exists but it has no long-lasting effect on capital structure. Indicating that the observed capital structures of publicly traded firms in Taiwan Stock Exchange aren¡¦t the outcomes that managers timed the equity market which is not identical to the perspectives of Baker and Wurgler (2002) and the speed of adjustment of capital structure of publicly traded firms in Taiwan Stock Exchange is very fast.

Thesis (M. Sc.)--University of Alberta, 2009. / Title from PDF file main screen (viewed on Dec. 14, 2009). "A thesis submitted to the Faculty of Graduate Studies and Research in partial fulfillment of the requirements for the degree of Master of Science, Department of Electrical and Computer Engineering, University of Alberta." Includes bibliographical references.

With the scaling of technology nodes, the speed performance of microprocessors has rapidly improved but the scaling of off-chip input/output (I/O) bandwidth is limited by physical pin resources and interconnect technologies. In order to reduce the performance gaps, new interface techniques have emerged and the marketplace has moved towards higher levels of integration with system on a chip (SoC) implementations. The advent of new techniques, however, has led to new challenges on the semiconductor and automated test equipment (ATE) industries. The relatively slow growing ATE technology comparing to I/O speeds especially intensifies manufacturing test issues. Testing high speed I/O timing parameters requires expensive high performance test equipment with high accuracy and resolution. The requirements increase integrated circuit (IC) manufacturing costs and thus test issues have become critical. This thesis focuses on on-chip test methods to improve test accuracy and reduce test costs for high speed double data rate (DDR) memory I/Os using source synchronous clocking. For testing the I/O timing parameters, a phase interpolator based on-chip timing sampler using a cycle-by-cycle control method was developed. This circuit generates data and clock patterns and controls the time delay between data and clock to detect the timing mismatch which indicates timing degradations. The on-chip timing sampler was implemented as a built-in self test (BIST) circuit for low-cost parametric timing measurements. The BIST scheme was fabricated with a 0.18-um CMOS process technology. Using the static and dynamic modes, measurement results are obtained for the I/O timing parameters such as the setup and hold times, input voltage-level variations tolerances, duty distortion tolerances and data skews. Moreover, a delay mismatch measurement method was developed to improve measurement accuracy using a simple control circuit. This delay mismatch detector measures timing mismatches between data and clock paths and then the timing mismatches are converted to timing specifications. This scheme is also implemented along with analog to digital converter (ADC) to collect digital test results supporting low-cost system-level tests. Thus, the low-frequency test results show that our on-chip measurement techniques provide an attractive low-cost solution and is effectively applied for testing high speed source synchronous systems. / text