The recent years have seen the revival of neo-Roman republicanism through the works of Philip Pettit, who has replaced Isaiah Berlin’s taxonomy of positive/negative liberty with freedom as nondomination. This essay compares the neo-Roman conception of nondomination to the liberal conception of noninterference, with the purpose of clarifying whether nondomination is a distinct concept of liberty and preferable to that of noninterference. The essay highlights the exchange between Pettit/Skinner and Carter/Kramer, wherein Carter and Kramer make their case for ‘pure negative liberty’, which is claimed to be the proper articulation of negative liberty. Pure-negative theorists believe that nondomination is a strand of negative liberty, adding nothing new to the concept, whereas their republican counterparts disagree. My essay argues that nondomination is a distinct, preferable concept of liberty, thanks to its view on fundamental unfreedom and the mere presence of arbitrary power, which the pure negative view fails to account for satisfactorily.

Testing is necessary factor to guarantee that ICs operate according to specifications before being delivered to customers. Testing is a process used to identify ICs containing imperfections or manufacturing defects that may cause failures. Inaccuracy and imperfections can be introduced during the fabrication of the chips due to the complex mechanical and chemical steps required during the manufacturing processes. The testing process step applies test patterns to circuits and analyzes their responses. This work focuses on VLSI circuit testing with two implementations for DFT (Design for testability); the first is an ATPG tool for sequential circuits and the second is a BIT (Built in Test) circuit for high frequency signal classification.There has been a massive increase in the number of transistors integrated in a chip, and the complexity of the circuit is increasing along with it. This growth has become a bottleneck for the test developers. The proposed ATPG tool was designed for testing sequential circuits. Scan Chains in Design For Testability (DFT) gained more prominence due to the increase in the complexity of the modern circuits. As the test time increases along with the number of memory elements in the circuit, new and improved methods are needed. Even though scan chains implementation effectively increases observability and controllability, a big portion of the time is wasted while shifting in and shifting out the test patterns through the scan chain. Additionally, the modern applications require operating speed at higher frequencies and there is a growing demand in testing equipment capable to test CMOS circuits utilized in high frequency applications.With the modern applications requiring operating speed at higher frequencies, there is a growing demand in testing equipment capable to test CMOS circuits utilized in high frequency applications. Two main problems have been associated when using external test equipment to test high frequency circuits; the effect of the resistance and capacitance of the probe on the performance of the circuit under test which leads to a faulty evaluation; and the cost of a dedicated high frequency tester. To solve these problems innovative test techniques are needed such as Built In Test (BIT) where self-evaluation takes place with a small area overhead and reduced requirements for external equipment. In the proposed methodology a Built In Test (BIT) detection circuit provides an efficient way to transform the high frequency response of the circuit under test into a DC signal.This work is focused in two major fields. The first topic is on VLSI circuit testing with two implementations for DFT (Design for testability); the first is an ATPG tool for sequential circuits and the second is a BIT (Built in Test) circuit for high frequency signal classification as explained. The second topic is focused on efficient implementations of arithmetic operations in arbitrary long numbers with emphasis to addition. Arbitrary-Precision arithmetic refers to a set of data structures and algorithms which allows to process much greater numbers that exceed the standard data types. . An application example where arbitrary long numbers are widely used is cryptography, because longer numbers offer higher encryption security. Modern systems typically employ up to 64-bit registers, way less than what an arbitrary number requires, while conventional algorithms do not exploit hardware characteristics as well. Mathematical models such as weather prediction and experimental mathematics require high precision calculations that exceed the precision found in most Arithmetic Logic Units (ALU). In this work, we propose a new scalable algorithm to add arbitrary long numbers. The algorithm performs bitwise logic operations rather than arithmetic on 64-bit registers. We propose two approaches of the same algorithm that utilize the same basic function created according to the rules of binary addition

京都大学 / 0048 / 新制・課程博士 / 博士(工学) / 甲第18284号 / 工博第3876号 / 新制||工||1595(附属図書館) / 31142 / 京都大学大学院工学研究科電子工学専攻 / (主査)教授 野田 進, 教授 川上 養一, 教授 藤田 静雄 / 学位規則第4条第1項該当 / Doctor of Philosophy (Engineering) / Kyoto University / DGAM

In this work the scattering of an incident plane wave propagating along a plane perpendicular to the xy-plane is studied. The wave is scattered from an infinitely long cylindrical object of arbitrary cross-section. Due to the arbitrary geometry of the obstacle, a finite differences numerical method is employed to approximate the solution of the scattering problems. The wave equation is expressed in terms of generalized curvilinear coordinates. Boundary conforming grids are generated using elliptic grid generators. Then, a explicit marching in time scheme is implemented over these grids. It is found that as time grows the numerical solution converges to a wave with harmonic time dependence. The amplitude of these waves is analyzed and graphed over generalized grids for different geometries. An important physical measure of the energy scattered, the differential scattering cross section, is also obtained. In particular, the method is applied to a circular cylindrical obstacle. For this case, the analytical solution can also be obtained by traditional spectral techniques. The method is validated by comparing this exact solution with the numerical approximation obtained from the application of it.

This thesis focuses on the generation and applications of stable optical frequency combs. Optical frequency combs are defined as equally spaced optical frequencies with a fixed phase relation among themselves. The conventional source of optical frequency combs is the optical spectrum of the modelocked lasers. In this work, we investigated alternative methods for optical comb generation, such as dual sine wave phase modulation, which is more practical and cost effective compared to modelocked lasers stabilized to a reference. Incorporating these comblines, we have generated tunable RF tones using the serrodyne technique. The tuning range was ±1 MHz, limited by the electronic waveform generator, and the RF carrier frequency is limited by the bandwidth of the photodetector. Similarly, using parabolic phase modulation together with time division multiplexing, RF chirp extension has been realized. Another application of the optical frequency combs studied in this thesis is real time data mining in a bit stream. A novel optoelectronic logic gate has been developed for this application and used to detect an 8 bit long target pattern. Also another approach based on orthogonal Hadamard codes have been proposed and explained in detail. Also novel intracavity modulation schemes have been investigated and applied for various applications such as a) improving rational harmonic modelocking for repetition rate multiplication and pulse to pulse amplitude equalization, b) frequency skewed pulse generation for ranging and c) intracavity active phase modulation in amplitude modulated modelocked lasers for supermode noise spur suppression and integrated jitter reduction. The thesis concludes with comments on the future work and next steps to improve some of the results presented in this work.

Aims. We consider the polarization arising from scattering in an envelope illuminated by a central anisotropic source. This work extends the theory introduced in a previous paper (Al-Malki et al. 1999) in which scattering polarization from a spherically symmetric envelope illuminated by an anisotropic point source was considered. Here we generalize to account for the more realistic expectation of a non-spherical envelope shape. Methods. Spherical harmonics are used to describe both the light source anisotropy and the envelope density distribution functions of the scattering particles. This framework demonstrates how the net resultant polarization arises from a superposition of three basic “shape” functions: the distribution of source illumination, the distribution of envelope scatterers, and the phase function for dipole scattering. Results. Specific expressions for the Stokes parameters and scattered flux are derived for the case of an ellipsoidal light source inside an ellipsoidal envelope, with principal axes that are generally not aligned. Two illustrative examples are considered: (a) axisymmetric mass loss from a rapidly rotating star, such as may apply to some Luminous Blue Variables, and (b) a Roche-lobe filling star in a binary system with a circumstellar envelope. Conclusions. As a general conclusion, the combination of source anisotropy with distorted scattering envelopes leads to more complex polarimetric behavior such that the source characteristics should be carefully considered when interpreting polarimetric data

N/A / Thesis / Master of Applied Science (MASc)

No description available.

No description available.

<p>Finite element analysis (FEA) employs a science-based approach in which the complete machining process can be simulated and optimized before resorting to costly and time-consuming experimental trials. In this work, cutting coefficient of AISI 1045 steel will be estimated using finite element modelling using Arbitrary Lagrangian Eulerian formulation (ALE). The estimated values are then experimentally validated. A parametric study is carried out after in order to investigate how some cutting parameters can affect the cutting coefficients. The process parameters to be varied include feed rate, cutting speed, and cutting edge radius.</p> / Master of Applied Science (MASc)