The purpose of this research is to develop fundamentals of compliant mechanisms in deployable space systems. The scope was limited to creating methods for thick origami, developing compliant deployable solar arrays, and developing methods for stowing and deploying the arrays. The research on actuation methods was focused on a one-time deployment of the array. Concepts for both passive and active actuation were considered. The primary objective of this work was to develop approaches to accommodate thickness in origami-based deployable arrays with a high ratio of deployed-to-stowed diameter. The HanaFlex design was derived from the origami flasher model and is developed as a deployable solar array for large arrays (150 kW or greater) and CubeSat arrays (60 W). The origami folding concept enables compact stowage of the array, which would be deployed from a hexagonal prism into a flat array with about a 10-times increase in deployed diameter as compared to stowed diameter. The work on the origami pattern for the solar array was also applied to the folding of 80-100 m2 solar sails for two NASA CubeSat missions, NEA-Scout and Lunar Flashlight. The CubeSat program is a promising avenue to put the solar array or solar sails into space for testing and proving their functionality. The deployable array concept is easily scalable, although application to CubeSats changes some of the design constraints. The thickness-to-diameter ratio is larger, making the issues of thickness more pronounced. Methods of actuation are also limited on CubeSats because of the rigorous size and weight constraints. This dissertation also includes the development of a compact, self-deploying array based on a tapered map fold design. The tapered map fold was modified by applying an elastic membrane to one side of the array and adequately spacing the panels adjacent to valley folds. Through this approach, the array can be folded into a fully dense stowed volume. Potential applications for the array include a collapsible solar array for military or backpacking applications. Additional compliant mechanism design was done in support of the HanaFlex array. This included a serpentine flexure to attach the array to the perimeter truss for deployment, and a bistable mechanism that may be used in the deployment of the array or sail.

Self assembled monolayers (SAMs) are widely used for surface modification. Alkylsilane monolayers are one of the most widely deposited and studied SAMs. My work focuses on the preparation, patterning, and application of alkysilane monolayers. 3-aminopropyltriethoxysilane (APTES) is one of the most popular silanes used to make active surfaces for surface modification. To possibly improve the surface physical properties and increase options for processing this material, I prepared and studied a series of amino silane surfaces on silicon/silicon dioxide from APTES and two other related silanes by chemical vapor deposition (CVD). I also explored CVD of 3-mercaptopropyltrimethoxysilane on silicon and quartz. Several deposition conditions were investigated. Results show that properties of silane monolayers are quite consistent under different conditions. For monolayer patterning, I developed a new and extremely rapid technique, which we termed laser activation modification of semiconductor surfaces or LAMSS. This method consists of wetting a semiconductor surface with a reactive compound and then firing a highly focused nanosecond pulse of laser light through the transparent liquid onto the surface. The high peak power of the pulse at the surface activates the surface so that it reacts with the liquid with which it is in contact. I also developed a new application for monolayer patterning. I built a technologically viable platform for producing protein arrays on silicon that appears to meet all requirements for industrial application including automation, low cost, and high throughput. This method used microlens array (MA) patterning with a laser to pattern the surface, which was followed by protein deposition. Stencil lithography is a good patterning technique compatible with monolayer modification. Here, I added a new patterning method and accordingly present a simple, straightforward procedure for patterning silicon based on plasma oxidation through a stencil mask. We termed this method subsurface oxidation for micropatterning silicon (SOMS).

No description available.

Electro-dynamic suspension (EDS) Magnetic levitation (Maglev) with its advantage in maintenance, safety, efficiency, speed, and noise is regarded as a leading candidate for the next generation transportation / space launch assist system. The Halbach array due to its unique magnetic field feature has been widely used in various applications. The EDS system using Halbach arrays leads to the potential EDS system without super-conductor (SC) technology. In this thesis, the Halbach array magnetic field and the dynamics of a novel Halbach array EDS Maglev system were considered. The practical Halbach array magnetic field was analyzed using both a Fourier series approach and the finite element method (FEM). In addition, the optimal Halbach array geometry was derived and analyzed. A novel active magnetic array was introduced and used in the Halbach array EDS Maglev configuration. Further more, since the system is self-regulated in lateral, roll, pitch, and yaw directions, the control was simplified and can be implemented electronically. The dynamic stability analysis and simulation results showed that the system is marginally stable and a control mechanism is needed for stability and ride comfort control. The six degree of freedom (DOF) dynamics, and the vehicle's mass center offset effects on those dynamics were investigated with multiple passive and active magnetic forces. The results indicated that the vehicle's mass center offset has a strong effect on the dynamics of the Maglev system due to the uniqueness of the magnetic force and also that the mass center offset can cause Maglev oscillations at the take off stage. In order to guarantee the dynamic stability and ride comfort of the Maglev system, an optimized active damping and a linear quadratic regulator (LQR) control were developed. Finally, the simulation confirmed the effectiveness of the proposed multi-input and multi-output (MIMO) control designs.

Reflectarrays are traditionally passive, planar microstrip antenna devices designed for reflected phase manipulation at each individual antenna element making up the array. By varying the phase response across the surface with the antenna elements, reflectarrays allows a planar surface to exhibit electromagnetically an arbitrary geometry, such as a spherical surface. Initially proposed as a low-cost replacement for bulky parabolic reflectors, reflectarrays have been successfully developed and utilized at both RF and millimeter-wave frequencies. From the standpoint of an optical systems designer, adapting low-frequency reflectarray technology to develop a sub-millimeter and infrared reflectarray (SMIR) would provide a highly desirable alternative to similarly behaved polished or diffractive optical devices. Compared to traditional optical reflectors, SMIRs should be cheaper to fabricate, have a smaller physical footprint, allow for utility stacking, and encourage direct integration of aberration correction. To demonstrate the feasibility of utilizing reflectarray technology at infrared (IR), a simple SMIR proof of concept has been successfully designed, fabricated, and tested. The SMIR is comprised of three independent arrays or "stripes" of a single size element on a coated optical flat. Actual reflectarray elements consist of variable size patches that exhibit higher operating bandwidths than reflectarrays utilizing other types of elements and are easier to fabricate at small dimensions. For testing, each stripe element has been chosen to exhibit a unique phase shift for measurement using an IR interferometer. Preliminary investigation of future reflectarray development is also discussed. Emphasis is placed on improving operating bandwidth, development of a planar focusing element, and aberration correction. With further development, SMIR technology should present a powerful tool for low cost, flexible optical system design.

In recent years, Light-emitting Diodes (LEDs) have become a promising candidate for backlighting Liquid Crystal Displays [1] (LCDs). Compared with traditional Cold Cathode Fluorescent Lamps (CCFLs) technology, LEDs offer not only better visual quality, but also improved power efficiency. However, to fully utilized LEDs' capability requires dynamic independent control of individual LEDs, which remains as a challenging topic. A FPGA-based hardware system for LED backlight control is proposed in this work. We successfully achieve dynamic adjustment of any individual LED's intensity in each of the three color channels (Red, Green and Blue), in response to a real time incoming video stream. In computing LED intensity, four video content processing algorithms have been implemented and tested, including averaging, histogram equalization, LED zone pattern change detection and non-linear mapping. We also construct two versions of the system. The first employs an embedded processor which performs the above-mentioned algorithms on pre-processed video data; the second embodies the same functionality as the first on fixed hardware logic for better performance and power efficiency. The system servers as the backbone of a consolidated display, which yields better visual quality than common commercial displays, we build in collaboration with a group of researchers from CREOL at UCF.

This Thesis describes the development of a cost-effective process for patterning nanoscale metal antenna arrays. Soft ultraviolet (UV) Nanoimprint Lithography (NIL) into bilayer resist was chosen since it enables repeatable large-scale replication of nanoscale patterns with good lift-off properties using a simple low-cost process. Nanofabrication often involves the use of Electron Beam Lithography (EBL) which enables the definition of nanoscale patterns on small sample regions, typically < 1 mm 2 . However its sequential nature makes the large scale production of nanostructured substrates using EBL cost-prohibitive. NIL is a pattern replication method that can reproduce nanoscale patterns in a parallel fashion, allowing the low-cost and rapid production of a large number of nanopatterned samples based on a single nanostructured master mold. Standard NIL replicates patterns by pressing a nanostructured hard mold into a soft resist layer on a substrate resulting in exposed substrate regions, followed by an optional Reactive Ion Etching (RIE) step and the subsequent deposition of e.g. metal onto the exposed substrate area. However, non-vertical sidewalls of the features in the resist layer resulting from an imperfect hard mold, from reflow of the resist layer, or from isotropic etching in the RIE step iii may cause imperfect lift-off. To overcome this problem, a bilayer resist method can be used. Using stacked resist layers with different etch rates, undercut structures can be obtained after the RIE step, allowing for easy lift-off even when using a mold with non-vertical sidewalls. Experiments were carried out using a nanostructured negative SiO2 master mold. Various material combinations and processing methods were explored. The negative master mold was transferred to a positive soft mold, leaving the original master mold unaltered. The soft mold consisted of a 5 m thick top Poly(methyl methacrylate) (PMMA), or Polyvinyl alcohol (PVA) layer, a 1.5 mm thick Polydimethylsiloxane (PDMS) buffer layer, and a glass supporting substrate. The soft mold was pressed into a bilayer of 300 nm PMMA and 350 nm of silicon based UV-curable resist that was spin-coated onto a glass slide, and cured using UV radiation. The imprinted patterns were etched using RIE, exposing the substrate, followed by metal deposition and lift-off. The experiments show that the use of soft molds enables successful pattern transfer even in the presence of small dust particles between the mold and the resist layer. Feature sizes down to 280 nm were replicated successfully

Graph theoretic modeling has served as an invaluable tool for solving a variety of problems since its introduction in Euler's paper on the Bridges of Königsberg in 1736 . Two amongst them of contemporary interest are the modeling of Redundant Arrays of Inexpensive Disks (RAID), and the identification of network attacks. While the former is vital to the protection and uninterrupted availability of data, the latter is crucial to the integrity of systems comprising networks. Both are of practical importance due to the continuing growth of data and its demand at increasing numbers of geographically distributed locations through the use of networks such as the Internet. The popularity of RAID has soared because of the enhanced I/O bandwidths and large capacities they offer at low cost. However, the demand for bigger capacities has led to the use of larger arrays with increased probability of random disk failures. This has motivated the need for RAID systems to tolerate two or more disk failures, without sacrificing performance or storage space. To this end, we shall first perform a comparative study of the existing techniques that achieve this objective. Next, we shall devise novel graph-theoretic algorithms for placing data and parity in arrays of n disks (n ≥ 3) that can recover from two random disk failures, for n = p - 1, n = p and n = 2p - 2, where p is a prime number. Each shall be shown to utilize an optimal ratio of space for storing parity. We shall also show how to extend the algorithms to arrays with an arbitrary number of disks, albeit with non-optimal values for the aforementioned ratio. The growth of the Internet has led to the increased proliferation of malignant applications seeking to breach the security of networked systems. Hence, considerable effort has been focused on detecting and predicting the attacks they perpetrate. However, the enormity of the Internet poses a challenge to representing and analyzing them by using scalable models. Furthermore, forecasting the systems that they are likely to exploit in the future is difficult due to the unavailability of complete information on network vulnerabilities. We shall present a technique that identifies attacks on large networks using a scalable model, while filtering for false positives and negatives. Furthermore, it also forecasts the propagation of security failures proliferated by attacks over time and their likely targets in the future.

Turbo codes are a recently discovered class of error correction codes that achieve near-Shannon limit performance. Because of their complexity and highly parallel nature, turbo-coded applications are well suited for configurable computing. Field-programmable gate arrays (FPGAs), which are the main building blocks of configurable computing machines (CCMs), allow users to design flexible hardware that is optimized for performance, speed, power consumption, and chip-area. This thesis presents the implementation and performance of an improved turbo decoder on a configurable computing platform. The design's performance and throughput are emphasized in light of its algorithmic improvements, and its flexibility is emphasized as it is ported to a newer, more efficient architecture with more hardware resources. Because this decoder will eventually become the error correction component of a software radio, the design must maintain a high data rate, interface easily with other modules, and conserve hardware resources for future research developments. / Master of Science

Deep neural networks (DNNs) are receiving immense attention because of their ability to solve complex problems. However, running a DNN requires a very large number of computations. Hence, dedicated hardware optimized for running deep learning algorithms known as neuromorphic architectures is often utilized. This dissertation focuses on evaluating andenhancing the accuracy of these neuromorphic architectures considering the designs of components, process variations, and adversarial attacks. The first contribution of the dissertation (Chapter 2) proposes design enhancements in analog Memristive Crossbar Array(MCA)-based neuromorphic architectures to improve classification accuracy. It introduces an analog Winner-Take-All (WTA) architecture and an on-chip training architecture. WTA ensures that the classification of the analog MCA is correct at the final selection level and the highest probability is selected. In particular, this dissertation presents a design of a highly scalable and precise current-mode WTA circuit with digital address generation. The design is based on current mirrors and comparators that use the cross-coupled latch structure. A post-silicon calibration circuit is also presented to handle process variations. On-chip training ensures that there is consistency in classification accuracy among different all analog MCA-based neuromorphic chips. Finally, an enhancement to the analog on-chip training architecture by implementing the Convolutional Neural Network (CNN) on MCA and software considerations to accelerate the training is presented.The second focus of the dissertation (Chapter 3) is on producing correct classification in the presence of malicious inputs known as adversarial attacks. This dissertation shows that MCA-based neuromorphic architectures ensure correct classification when the input is compromised using existing adversarial attack models. Furthermore, it shows that adversarialrobustness can be further improved by compression-based preprocessing steps that can be implemented on MCAs. It also evaluates the impact of the architecture in Chapter 2 under adversarial attacks. It shows that adversarial attacks do not uniformly affect the classification accuracy of different MCA-based chips. Experimental evidence using a variety of datasets and attack models supports the impact of MCA-based neuromorphic architectures and compression-based preprocessing implemented on MCAs to mitigate adversarial attacks. It is also experimentally shown that the on-chip training improves consistency in mitigating adversarial attacks among different chips. The final contribution (Chapter 4) of this dissertation introduces an enhancement of the method in Chapter 3. It consists of input preprocessing using compression and subsequent rescale and rearrange operations that are implemented using MCAs. This approach further improves the robustness against adversarial attacks. The rescale and rearrange operations are implemented using a DNN consisting of fully connected and convolutional layers. Experimental results show improved defense compared to similar input preprocessing techniques on MCAs.