The next generation of wireless communications will demand the use of software radio technology as the basic architecture to support multi-standard, multi-mode and future-proof radio designs. Software-defined radios are configurable devices in which the physical layer can be reprogrammed to support various standards. Field programmable architectures provide a suitable platform to achieve such run-time reconfigurations of the physical layer of the radio. This thesis explores the use of FPGAs in the design of reconfigurable radios. The results presented here demonstrate how FPGAs can be used to provide the flexibility, performance, efficiency and better resource utilization while meeting the speed and area constraints set by a particular design. The partial reconfiguration feature available in the state-of-the art FPGAs has been exploited to implement the baseband physical layer of reconfigurable radio which can be altered to support various modulations schemes for different wireless standards. The design flow for partial reconfiguration along with the implementation results on two different FPGA platforms is presented. The experiments presented in this thesis make use of System Generator for DSP, a productivity tool from Xilinx, to design and to simulate system-level models in a MATLAB/Simulink environment, and to obtain timing and resource utilization results before implementing the design on actual hardware. / Master of Science

Scientific solutions to physical problems are computationally intensive. With the increasing emphasis in the area of Custom Computing Machines, many physical problems are being solved using configurable computers. The Finite Element Method (FEM) is an efficient way of solving physical problems such as heat equations, stress analysis and two- and three-dimensional Poisson's equations. This thesis presents the solution to physical problems using the FEM on a configurable platform. The core computational unit in an iterative solution to the FEM, the matrix-by-vector multiplication, is developed in this thesis along with the framework necessary for implementing the FEM solution. The solutions for 2-D and 3-D Poisson's equations are implemented with the use of an adaptive mesh refinement method. The dominant computation in the method is matrix-by-vector multiplication and is performed on the Wildforce board, a configurable platform. The matrix-by-vector multiplication units developed in this thesis are basic mathematical units implemented on a configurable platform and can be used to accelerate any mathematical solution that involves such an operation. / Master of Science

FPGA implementation tools have not kept pace with growing FPGA density. It is common for non-trivial designs to take multiple hours to go through the entire FPGA toolflow (synthesis, mapping, placement, routing, bitstream generation). FPGA implementation tool runtime is a major hindrance to FPGA Productivity. In modern FPGA designs, designers often change logic and/or connections in an already existing design. If small modifications are made to a particular module in a design, then almost the entire design will go through most of the FPGA toolflow again. This can be time consuming for complex designs and hinder productivity of FPGA designers. The main goal of this thesis is to improve FPGA productivity by reducing FPGA design implementation time for modifications made to an already existing design for rapid system deployment. In this thesis, a toolkit is presented, which is capable of making design modifications at a lower level of abstraction for already existing designs on Xilinx FPGAs. The toolkit is a part of the open-source RapidSmith framework and includes the EDIF parser, mapper, placer, and router. It can be used to change logic and/or modify connections. Modules can be placed, unplaced, relocated, and/or duplicated with ease using this toolkit. Significant time-savings were seen by making use of the toolkit along-with the standard Xilinx FPGA toolflow, for making design modifications to already existing designs. / Master of Science

Data security is becoming ever more important in embedded and portable electronic devices. The sophistication of the analysis techniques used by attackers is amazingly advanced. Digital devices' external interfaces to memory and communications interfaces to other digital devices are vulnerable to malicious probing and examination. A hostile observer might be able to glean important details of a device's design from such an interface analysis. Defensive measures for protecting a device must therefore be even more sophisticated and robust. This thesis presents an architecture that acts as a secure wrapper around an embedded application on a Field Programmable Gate Array (FPGA). The architecture includes functional units that serve to authenticate a user over a secure serial interface, create a key with multiple layers of security, and encrypt an external memory interface using that key. In this way, the wrapper protects all of the digital interfaces of the embedded application from external analysis. Cryptographic methods built into the system include an RSA-related secure key exchange, the Secure Hash Algorithm, a certificate storage system, and the Data Encryption Standard algorithm in counter mode. The principles behind the encrypted external memory interface and the secure authentication interface can be adjusted as needed to form a secure wrapper for a wide variety of embedded FPGA applications. / Master of Science

A very basic engineering tradeoff is performance versus flexibility and this design choice must be made when developing a software radio. Hardware devices such as General Purpose Processors (GPPs), Digital Signal Processors (DSPs), Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs) all provide a designer with choices along the performance versus flexibility spectrum. The designer must choose a combination of GPP, DSP, FPGA and ASIC devices to balance the needs of performance versus flexibility. The Software Communications Architecture (SCA) is a specification for a software radio architecture produced by the Joint Program Executive Office (JPEO) Joint Tactical Radio System (JTRS). The 2.2 revision of the SCA only implies support for GPPs, with no specified support for additional devices such as FPGAs. However, FPGA integration within the scope of the SCA is still possible. The integration of an additional processing hardware device other than a GPP requires the ability to logically represent the device within the Core Framework. This representation is implemented within the OSSIE Core Framework, an open source implementation of the SCA. The representation requires the support of multiple implementations of signal processing components within the framework, a simple component deployment model, and the abstraction of the FPGA interactions into a software component. / Master of Science

Turbo codes are a new class of codes that can achieve exceptional error performance and energy efficiency at low signal-to-noise ratios. Decoding turbo codes is a complicated procedure that often requires custom hardware if it is to be performed at acceptable speeds. Configurable computing machines are able to provide the performance advantages of custom hardware while maintaining the flexibility of general-purpose microprocessors and DSPs. This thesis presents an implementation of a turbo decoder on an FPGA-based configurable computing platform. Portability and flexibility are emphasized in the implementation so that the decoder can be used as part of a configurable software radio. The system presented performs turbo decoding for a variable block size with a variable number of decoding iterations while using only a single FPGA. When six iterations are performed, the decoder operates at an information bit rate greater than 32 kbps. / Master of Science

As technology evolves and new methods for designing radios arise, it becomes necessary to continue the search for fast and flexible development environments. Some of these new technologies include software defined radio (SDR), Field Programmable Gate Arrays (FPGAs), and the open source project GNU Radio. Software defined radio is a concept that GNU Radio has harnessed to allow developers to quickly create flexible radio designs. In terms of hardware, the maturity of FPGAs give radio designers new opportunities to develop high-speed radios having high-throughput and low-latency, yet the conventional build-time for FPGAs is a limiting factor for productivity. Recent research has lead to reductions in build-time by using FPGAs in a non-traditional manner, meaning productivity no longer has to be sacrificed. The AgileHW project demonstrated this concept and will be used as a basis to develop an overlaying architecture that uses a combination of the technologies mentioned to create a flexible, open, and efficient environment for radio development. This thesis discusses the realization of this architecture with the use of Xilinx FPGAs as a hardware accelerator for an enhanced GNU Radio. / Master of Science

This thesis investigates the design and the performance of low-power microsensors that communicate directly to a satellite or a constellation of satellites. Information is spread using pseudo noise (PN) or Barker codes. The sensors use a single circular microstrip patch element with a wide beamwidth or a miniature phased array antenna that continuously scans to access the satellite(s). The array beam is controlled with a beam-forming network (BFN), which contains 3 or 4-bit phase shifters, which can be made in micro-electro-mechanical systems (MEMS) or in monolithic microwave integrated circuits (MMIC). The antennas are designed using array simulation program called 'ARRAY' and the results are used in another simulation program called Advanced Design System (ADS) to simulate the whole sensor package that uses one of the antennas. The simulation results show that a sensor as small as 2.35 cm in diameter is able to send information with data rate of 1 kbps at bit error rate less than 10?? to low-earth orbit (LEO) satellites with a transmitted power of 27.5 microwatts (-15.6 dBm). / Master of Science

This thesis investigates optical feed methods for phased array antennas. The technical and practical limitations are analyzed and an optimum design is determined. This optimum optical feed is a two-beam interferometric approach which uses acoustooptic phase control. The theory is derived; a computer model is developed; and the limitations are determined. Design modifications are suggested which reduce limitations and greatly extend the range of applications. / Master of Science

Precise radiation pattern control for an array antenna requires precise control of array element excitations. One application is that of low side lobe patterns. Classical synthesis methods for the desired pattern may not be realized in practice due to coupling effects. Coupling occurs in two forms: the mutual coupling between array elements and the coupling introduced by the feed networks. Ideally one could account for such coupling within the array architecture during the design process and alter the feed network parameters to adjust for such coupling. Unfortunately, this is a nonlinear problem requiring special solution techniques. This report presents the solution techniques for determining feed network parameter values that compensate for antenna-feed network coupling. Scattering parameter representations of the antenna array and the feed networks are used. Examples of various array configurations for microstrip antenna arrays and for dipole arrays are included. / Master of Science