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Micro data flow processor designChang, Chih-ming 24 September 1993 (has links)
Computer has evolved rapidly during the past several decades in terms of
its implementation technology; it's architecture, however, has not changed dramatically
since the von Neumann computer(control flow) model emerged in the 1940s. One
main reason is that the performance for this kind of computers was able to satisfy
the requirement of most users. Another reason maybe that the engineers who designed
them are more familiar with this model. However, recent solutions to the problem
of parallelizing sequential nature instructions on a von Neumann machine complicate
both the compiler and the controller design. Therefore, another computer model, namely
the data flow model, has regained attention since this model of computation exposes
parallelism inherent in the program naturally.
In terms of implementation methodology, we currently use synchronous sequential
logic, which is clock controlled for synchronization within circuits. This design
philosophy becomes hard to follow due to the occurrence of clock skew as the clock
frequency goes higher and higher. One way to eliminate these clock related problems
is to use the self-timed(asynchronous) implementation methodology. It features advantages
such as free of clock-skew, low power consumption, composibility and so forth.
Since data flow(data driven) computation model provides the execution of instructions
asynchronously, it is natural to implement a data flow processor using self-timed circuits.
In this thesis, micro pipelines, one of the self-timed implementation methodology,
is used to implement a preliminary version of general purpose static data flow
processor. Some interesting observations will be addressed in this thesis. An example
program of general difference recursive equation is given to test the correctness and
performance of this processor. We hope to gain more insight on how to design and
implement self-timed systems in the future. / Graduation date: 1994
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Design of an asynchronous third-order finite impulse response filterOren, Joel A. 08 February 1994 (has links)
With the increased demand for complex digital signal processing systems,
real-time signal processing requires higher throughput systems. In the past, the
throughput has been increased by increasing the clock rates, but
synchronization can become increasingly more difficult. Recently there has
been renewed interest in designing asynchronous digital systems. In an
asynchronous system, there is no global clock, and all modules communicate
through handshaking. In this thesis we demonstrate an implementation of an
FIR filter using asynchronous digital circuit techniques. These asynchronous
design techniques are used to test whether a practical signal processing filter
can be implemented with asynchronous logic. A third-order four-bit filter is
developed and simulated with SPICE, comparing favorably with other available
technologies in speed and power consumption. Although in practice 8-16 bits
are needed, this work is sufficient to demonstrate the feasibility of asynchronous
circuits for filtering applications. A chip is laid out in 2 micron CMOS, and
testing shows that it has a speed-power product comparable with asynchronous
designs fabricated by others. / Graduation date: 1994
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Delay-insensitive ternary logic (DITL)Parameswaran Nair, Ravi Sankar, January 2007 (has links) (PDF)
Thesis (M.S.)--University of Missouri--Rolla, 2007. / Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 27, 2007) Includes bibliographical references (p. 55-56).
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Generic algorithms and NULL Convention Logic hardware implementation for unsigned and signed quad-rail multiplicationMallepalli, Samarsen Reddy, January 2007 (has links) (PDF)
Thesis (M.S.)--University of Missouri--Rolla, 2007. / Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 27, 2007) Includes bibliographical references (p. 66-67).
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Asynchronous nanowire crossbar architecture for manufacturability, modularity and robustnessBonam, Ravi Kiran, January 2008 (has links) (PDF)
Thesis (M.S.)--Missouri University of Science and Technology, 2008. / Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed April 28, 2008) Includes bibliographical references.
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Asynchronous control circuit design and hazard generation : inertial delay and pure delay models /Tabrizi, Nozar. January 1997 (has links) (PDF)
Thesis (Ph.D.) -- University of Adelaide, Dept. of Electrical and Electronic Engineering, 1997. / Bibliography: leaves 158-167.
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Learning, probabilistic, and asynchronous technologies for an ultra efficient datapathMarr, Bo. January 2009 (has links)
Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010. / Committee Chair: Paul Hasler; Committee Co-Chair: David V. Anderson. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Simulation and modeling of substrate noise generation from synchronous and asynchronous digital logic circuits /Hanken, Christopher. January 1900 (has links)
Thesis (M.S.)--Oregon State University, 2008. / Printout. Includes bibliographical references (leaves 57-59). Also available on the World Wide Web.
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Circuitos assíncronos na plataforma FPGAMocho, Renato Ubiratan Reis January 2006 (has links)
Os circuitos digitais cada vez mais são exigidos quanto ao desempenho e modularidade nos processos dos dias atuais. Para resolver estes processos, o comércio utiliza largamente circuitos digitais síncronos, que se baseiam no controle do sincronismo através de um relógio central. Esses circuitos, apesar de serem de fácil implementação e terem uma metodologia já conhecida, apresentam limitações quando se considera a distribuição dos sinais de sincronismo, a interferência do meio e os possíveis atrasos. Os circuitos assíncronos apresentam uma solução natural a essas exigências, uma vez que, possuem independência do sinal do relógio e toda sua construção é modular. Este trabalho apresenta um estudo comparativo de alguns estilos de projetos para construção de circuitos assíncronos utilizando dispositivos programados por lógica, PLDs, utilizando ferramentas de síntese lógica comerciais para circuitos síncronos. Esses circuitos assíncronos são descritos em VHDL para as células Muller, elementos M de N, registrador assíncrono, somadores e circuitos mais complexos em anel assíncrono e implementados em CPLDs e FPGAs. Os circuitos mais complexos são construídos em quatro estilos de projeto para os circuitos dos somadores: Descrição comportamental com indicação forte do sinal, DIMS, NCL e derivação a partir de circuito combinacional síncrono. Através dessa avaliação foi possível verificar as tendências do custo de elementos de programação e atrasos para realização de cálculos, frente aos circuitos síncronos similares. / This work presents a study about the implementation of asynchronous circuits on programmable devices platform. It investigates four different ways of implementing asynchronous circuits, including implementation of several different circuits in platforms provided by three different manufacturers. The implemented asynchronous circuits have a very poor performance when compared to their synchronous counterpart. However, this was expected as the platforms used were developed to be used with synchronous designs. The contributions of this work are in the following areas. First, it was described in detail how to implement VHDL code for self-timed designs. Second, different design were implemented to test the VHDL descriptions in the chosen platforms. Third, by comparing four different asynchronous styles, it is possible to find a style that is the more adequate for use in current FPGAs. Fourth, by analyzing the results obtained, it was possible to derive some conclusions on why asynchronous designs are so costly for these platforms and derive some suggestions to be used in the implementation of asynchronous FPGAs.
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Circuitos assíncronos na plataforma FPGAMocho, Renato Ubiratan Reis January 2006 (has links)
Os circuitos digitais cada vez mais são exigidos quanto ao desempenho e modularidade nos processos dos dias atuais. Para resolver estes processos, o comércio utiliza largamente circuitos digitais síncronos, que se baseiam no controle do sincronismo através de um relógio central. Esses circuitos, apesar de serem de fácil implementação e terem uma metodologia já conhecida, apresentam limitações quando se considera a distribuição dos sinais de sincronismo, a interferência do meio e os possíveis atrasos. Os circuitos assíncronos apresentam uma solução natural a essas exigências, uma vez que, possuem independência do sinal do relógio e toda sua construção é modular. Este trabalho apresenta um estudo comparativo de alguns estilos de projetos para construção de circuitos assíncronos utilizando dispositivos programados por lógica, PLDs, utilizando ferramentas de síntese lógica comerciais para circuitos síncronos. Esses circuitos assíncronos são descritos em VHDL para as células Muller, elementos M de N, registrador assíncrono, somadores e circuitos mais complexos em anel assíncrono e implementados em CPLDs e FPGAs. Os circuitos mais complexos são construídos em quatro estilos de projeto para os circuitos dos somadores: Descrição comportamental com indicação forte do sinal, DIMS, NCL e derivação a partir de circuito combinacional síncrono. Através dessa avaliação foi possível verificar as tendências do custo de elementos de programação e atrasos para realização de cálculos, frente aos circuitos síncronos similares. / This work presents a study about the implementation of asynchronous circuits on programmable devices platform. It investigates four different ways of implementing asynchronous circuits, including implementation of several different circuits in platforms provided by three different manufacturers. The implemented asynchronous circuits have a very poor performance when compared to their synchronous counterpart. However, this was expected as the platforms used were developed to be used with synchronous designs. The contributions of this work are in the following areas. First, it was described in detail how to implement VHDL code for self-timed designs. Second, different design were implemented to test the VHDL descriptions in the chosen platforms. Third, by comparing four different asynchronous styles, it is possible to find a style that is the more adequate for use in current FPGAs. Fourth, by analyzing the results obtained, it was possible to derive some conclusions on why asynchronous designs are so costly for these platforms and derive some suggestions to be used in the implementation of asynchronous FPGAs.
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