Purpose – This report aims to address the methods used to obtain multi-regional input-output tables (MRIO-tables). Method – The research focuses on three gravity model of trade methods: simple gravity model estimation, doubly constrained gravity model estimation, and gravity model estimation with calibrated error function minimization. These methods are used for estimating and modelling multiregional trade flows, specifically in the context of MRIO-tables. These methods will be denoted as method 1, method 2 and method 3. Through a comparative analysis, the study focuses on the strengths and limitations of these methods and provides valuable insights for policymakers and researchers in the field. The findings contribute to a better understanding of the differences between the methods and their effectiveness in accurately representing MRIO-tables. Findings – This study evaluates three methods (mentioned above) for estimating multiregional trade flows, highlighting their performance. Method 1 and 2, exhibited similarities in their approach to estimating trade flows, both surpassing the performance of method 3 across various evaluation metrics. According to the results, method 1 and 2 are better than method 3 in accurately estimating multiregional trade flows. Limitations – This work had some limitations, the research focused on one specific product and how they flow between and across the regions as well as the total quantity of this product, i.e., the margins.

This dissertation is the result of research and development of a power conditioning system for Superconductive Magnetic Energy Storage System. The dominant challenge of this research was to develop the power conditioning system that can match slowly varying dc voltage and dc current on the super conductive magnet side with the ac voltages and ac currents on the utility side. At the same time the power conditioning system was required to provide a bi-directional power flow to the superconductive magnet. The focus of this dissertation is a three-level diode clamped dc-ac converter which is a principle part of the power conditioning system. Accordingly, this dissertation deals with the space vector modulation of three-level converters and introduces a computationally very efficient three-level space vector modulation algorithm that is experimentally verified. Furthermore, the proposed space vector modulation algorithm is successfully generalized to allow equally efficient, real time implementation of space vector modulation to dc-ac converters with virtually any number of levels. The most important advantage of the proposed concept is in the fact that the number of instructions required to implement the algorithm is almost independent from the number of levels in a multilevel converter. More on the side of the control of multilevel converters, the particular attention in this dissertation is paid to the problem of charge balance in the split dc-link capacitors of three-level neutral-point-clamped converters. It is a known fact that although the charge balance in the neutral point can be maintained on a line cycle level, a significant third harmonic current flows into the neutral point for certain loading conditions, causing the neutral point voltage ripple. The logical consequence of that ripple is the deteriorated quality of the output voltage waveforms as well as the increased voltage stress on the switching devices. This was the motivation to more carefully explore the loading conditions that cause the unbalance, as well as to study the fundamental limitations of dc-link capacitor charge balancing algorithms. As a part of that work, a new model of the neutral point current in the rotating coordinate frame is developed as a tool in investigation of theoretical limitations and in providing some intuitive insight into the problem. Additionally, the low frequency ripple is quantified and guidelines are offered that can help size the dc-link capacitors. Because the study of the neutral point balance identified the loading conditions, that under some possible system constraints, cause an unavoidable neutral point voltage ripple, a feed forward type of control method is developed next. The proposed feed forward algorithm can effectively prevent the neutral point voltage ripple from creating distortions in the converter output voltage under all loading conditions and without causing additional disturbance in the neutral point voltage. The feed forward method is developed for a sine triangle as well as for the space vector type PWM algorithm. The simulation results that include the full dynamic model of the converter and load system validate the feed forward approach and prove that the feed forward algorithm can effectively compensate the effect of the neutral point voltage ripple. The simulation results are than experimentally verified. / Ph. D.

High availability is a critical feature of data centers, cloud, and cluster computing environments. Replication is a classical approach to increase service availability by providing redundancy. However, traditional replication methods are increasingly unattractive for deployment due to several limitations such as application-level non-transparency, non-isolation of applications (causing security vulnerabilities), complex system management, and high cost. Virtualization overcomes these limitations through another layer of abstraction, and provides high availability through virtual machine (VM) live migration: a guest VM image running on a primary host is transparently check-pointed and migrated, usually at a high frequency, to a backup host, without pausing the VM; the VM is resumed from the latest checkpoint on the backup when a failure occurs. A virtual cluster (VC) generalizes the VM concept for distributed applications and systems: a VC is a set of multiple VMs deployed on different physical machines connected by a virtual network. This dissertation presents a set of VM live migration techniques, their implementations in the Xen hypervisor and Linux operating system kernel, and experimental studies conducted using benchmarks (e.g., SPEC, NPB, Sysbench) and production applications (e.g., Apache webserver, SPECweb). We first present a technique for reducing VM migration downtimes called FGBI. FGBI reduces the dirty memory updates that must be migrated during each migration epoch by tracking memory at block granularity. Additionally, it determines memory blocks with identical content and shares them to reduce the increased memory overheads due to block-level tracking granularity, and uses a hybrid compression mechanism on the dirty blocks to reduce the migration traffic. We implement FGBI in the Xen hypervisor and conduct experimental studies, which reveal that the technique reduces the downtime by 77% and 45% over competitors including LLM and Remus, respectively, with a performance overhead of 13%. We then present a lightweight, globally consistent checkpointing mechanism for virtual cluster, called VPC, which checkpoints the VC for immediate restoration after (one or more) VM failures. VPC predicts the checkpoint-caused page faults during each checkpointing interval, in order to implement a lightweight checkpointing approach for the entire VC. Additionally, it uses a globally consistent checkpointing algorithm, which preserves the global consistency of the VMs' execution and communication states, and only saves the updated memory pages during each checkpointing interval. Our Xen-based implementation and experimental studies reveal that VPC reduces the solo VM downtime by as much as 45% and reduces the entire VC downtime by as much as 50% over competitors including VNsnap, with a memory overhead of 9% and performance overhead of 16%. The dissertation's third contribution is a VM resumption mechanism, called VMresume, which restores a VM from a (potentially large) checkpoint on slow-access storage in a fast and efficient way. VMresume predicts and preloads the memory pages that are most likely to be accessed after the VM's resumption, minimizing otherwise potential performance degradation due to cascading page faults that may occur on VM resumption. Our experimental studies reveal that VM resumption time is reduced by an average of 57% and VM's unusable time is reduced by 73.8% over native Xen's resumption mechanism. Traditional VM live migration mechanisms are based on hypervisors. However, hypervisors are increasingly becoming the source of several major security attacks and flaws. We present a mechanism called HSG-LM that does not involve the hypervisor during live migration. HSG-LM is implemented in the guest OS kernel so that the hypervisor is completely bypassed throughout the entire migration process. The mechanism exploits a hybrid strategy that reaps the benefits of both pre-copy and post-copy migration mechanisms, and uses a speculation mechanism that improves the efficiency of handling post-copy page faults. We modify the Linux kernel and develop a new page fault handler inside the guest OS to implement HSG-LM. Our experimental studies reveal that the technique reduces the downtime by as much as 55%, and reduces the total migration time by as much as 27% over competitors including Xen-based pre-copy, post-copy, and self-migration mechanisms. In a virtual cluster environment, one of the main challenges is to ensure equal utilization of all the available resources while avoiding overloading a subset of machines. We propose an efficient load balancing strategy using VM live migration, called DCbalance. Differently from previous work, DCbalance records the history of mappings to inform future placement decisions, and uses a workload-adaptive live migration algorithm to minimize VM downtime. We improve Xen's original live migration mechanism and implement the DCbalance technique, and conduct experimental studies. Our results reveal that DCbalance reduces the decision generating time by 79%, the downtime by 73%, and the total migration time by 38%, over competitors including the OSVD virtual machine load balancing mechanism and the DLB (Xen-based) dynamic load balancing algorithm. The dissertation's final contribution is a technique for VM live migration in Wide Area Networks (WANs), called FDM. In contrast to live migration in Local Area Networks (LANs), VM migration in WANs involve migrating disk data, besides memory state, because the source and the target machines do not share the same disk service. FDM is a fast and storage-adaptive migration mechanism that transmits both memory state and disk data with short downtime and total migration time. FDM uses page cache to identify data that is duplicated between memory and disk, so as to avoid transmitting the same data unnecessarily. We implement FDM in Xen, targeting different disk formats including raw and Qcow2. Our experimental studies reveal that FDM reduces the downtime by as much as 87%, and reduces the total migration time by as much as 58% over competitors including pre-copy or post-copy disk migration mechanisms and the disk migration mechanism implemented in BlobSeer, a widely used large-scale distributed storage service. / Ph. D.

This dissertation presents voltage stabilization techniques for flying capacitors used in soft-switching multilevel active power filters. The proposed active filter has proved to be a solution for power system harmonics produced by static high power converters. However, voltage unbalance of the clamping capacitors in the active filter in practical applications was observed due to its unequal parameters. Thus, the fundamentals of flying capacitors were characterized dealing with voltage balancing between flying capacitors and dc capacitors under practical operation, rather than ideal conditions. The study of voltage balancing provides the fundamental high-level solutions to flying capacitor based multilevel converter and inverter applications without additional passive balancing circuits. The use of proposed voltage balancing techniques made it possible to have a simple structure for solving the problems associated with the conventional bulky passive resistors and capacitor banks. Furthermore, the proposed control algorithms can be implemented with a real time digital signal processor. It can achieve the high performance of the active filter by compensating an adaptive gain to the controller. The effectiveness of the proposed controller was confirmed through various simulations and experiments. The focus of this study is to identify and develop voltage stabilization techniques for flying capacitors used in a proposed active filter. The voltage unbalance is investigated and characterized to provide safe operations. After having defined the problems associated with the voltage unbalance, the most important voltage stabilization techniques are proposed to solve this problem, in conjunction with an instantaneous reactive power (IRP) control of an active filter. In order to reduce the switching losses and improve the efficiency of the active filter, the proposed soft-switching techniques were evaluated through simulation and experimentation. Experimental results indicate that the proposed active filter achieved zero-voltage conditions in all of the main switches and zero-current turn-off conditions to the auxiliary switches during commutation processes. Also, various studies on soft-switching techniques, multilevel inverters, control issues and dynamics of the proposed active filter are discussed and analyzed in depth. / Ph. D.

This dissertation investigates novel statistical approaches for causal effect estimation in observational settings, where controlled experimentation is infeasible and confounding is the main hurdle in estimating causal effect. As such, deconfounding constructs the main subject of this dissertation, that is (i) to restore the covariate balance between treatment groups and (ii) to attenuate spurious correlations in training data to derive valid causal conclusions that generalize. By incorporating ideas from representation learning, adversarial matching, generative causal estimation, and invariant risk modeling, this dissertation establishes a causal framework that balances the covariate distribution in latent representation space to yield individualized estimations, and further contributes novel perspectives on causal effect estimation based on invariance principles. The dissertation begins with a systematic review and examination of classical propensity score based balancing schemes for population-level causal effect estimation, presented in Chapter 2. Three causal estimands that target different foci in the population are considered: average treatment effect on the whole population (ATE), average treatment effect on the treated population (ATT), and average treatment effect on the overlap population (ATO). The procedure is demonstrated in a naturalistic driving study (NDS) to evaluate the causal effect of cellphone distraction on crash risk. While highlighting the importance of adopting causal perspectives in analyzing risk factors, discussions on the limitations in balance efficiency, robustness against high-dimensional data and complex interactions, and the need for individualization are provided to motivate subsequent developments. Chapter 3 presents a novel generative Bayesian causal estimation framework named Balancing Variational Neural Inference of Causal Effects (BV-NICE). Via appealing to the Robinson factorization and a latent Bayesian model, a novel variational bound on likelihood is derived, explicitly characterized by the causal effect and propensity score. Notably, by treating observed variables as noisy proxies of unmeasurable latent confounders, the variational posterior approximation is re-purposed as a stochastic feature encoder that fully acknowledges representation uncertainties. To resolve the imbalance in representations, BV-NICE enforces KL-regularization on the respective representation marginals using Fenchel mini-max learning, justified by a new generalization bound on the counterfactual prediction accuracy. The robustness and effectiveness of this framework are demonstrated through an extensive set of tests against competing solutions on semi-synthetic and real-world datasets. In recognition of the reliability issue when extending causal conclusions beyond training distributions, Chapter 4 argues ascertaining causal stability is the key and introduces a novel procedure called Risk Invariant Causal Estimation (RICE). By carefully re-examining the relationship between statistical invariance and causality, RICE cleverly leverages the observed data disparities to enable the identification of stable causal effects. Concretely, the causal inference objective is reformulated under the framework of invariant risk modeling (IRM), where a population-optimality penalty is enforced to filter out un-generalizable effects across heterogeneous populations. Importantly, RICE allows settings where counterfactual reasoning with unobserved confounding or biased sampling designs become feasible. The effectiveness of this new proposal is verified with respect to a variety of study designs on real and synthetic data. In summary, this dissertation presents a flexible causal inference framework that acknowledges the representation uncertainties and data heterogeneities. It enjoys three merits: improved balance to complex covariate interactions, enhanced robustness to unobservable latent confounders, and better generalizability to novel populations. / Doctor of Philosophy / Reasoning cause and effect is the innate ability of a human. While the drive to understand cause and effect is instinct, the rigorous reasoning process is usually trained through the observation of countless trials and failures. In this dissertation, we embark on a journey to explore various principles and novel statistical approaches for causal inference in observational studies. Throughout the dissertation, we focus on the causal effect estimation which answers questions like ``what if" and ``what could have happened". The causal effect of a treatment is measured by comparing the outcomes corresponding to different treatment levels of the same unit, e.g. ``what if the unit is treated instead of not treated?". The challenge lies in the fact that i) a unit only receives one treatment at a time and therefore it is impossible to directly compare outcomes of different treatment levels; ii) comparing the outcomes across different units may involve bias due to confounding as the treatment assignment potentially follows a systematic mechanism. Therefore, deconfounding constructs the main hurdle in estimating causal effects. This dissertation presents two parallel principles of deconfounding: i) balancing, i.e., comparing difference under similar conditions; ii) contrasting, i.e., extracting invariance under heterogeneous conditions. Chapter 2 and Chapter 3 explore causal effect through balancing, with the former systematically reviews a classical propensity score weighting approach in a conventional data setting and the latter presents a novel generative Bayesian framework named Balancing Variational Neural Inference of Causal Effects(BV-NICE) for high-dimensional, complex, and noisy observational data. It incorporates the advance deep learning techniques of representation learning, adversarial learning, and variational inference. The robustness and effectiveness of the proposed framework are demonstrated through an extensive set of experiments. Chapter 4 extracts causal effect through contrasting, emphasizing that ascertaining stability is the key of causality. A novel causal effect estimating procedure called Risk Invariant Causal Estimation(RICE) is proposed that leverages the observed data disparities to enable the identification of stable causal effects. The improved generalizability of RICE is demonstrated through synthetic data with different structures, compared with state-of-art models. In summary, this dissertation presents a flexible causal inference framework that acknowledges the data uncertainties and heterogeneities. By promoting two different aspects of causal principles and integrating advance deep learning techniques, the proposed framework shows improved balance for complex covariate interactions, enhanced robustness for unobservable latent confounders, and better generalizability for novel populations.

The electric power system is undergoing a paradigm change on how electric energy is generated, transmitted, and delivered. Power electronics systems which can provide medium-voltage (MV) to high-voltage (HV) output (>13.8 kV ac, > 20 kV dc) with much faster dynamic response (> 10 kHz bandwidth) or high switching-frequency will enable new electronic energy network architectures, like MVDC power delivery, underground solid-state power substation (SSPS), and high-density power electronics building block (PEBB); help drive the levelized cost of electricity (LCOE) of renewable energy on par with conventional power generation; deliver precise and clean power to loads like high-speed electric motors; push the future power system toward 100% renewable energy and energy storage supplied. In the MV to HV area, the power conversion solution is dominated by silicon devices, like SCR, IGCT, and IGBT, which are slow in nature, posing significant switching losses and bulky auxiliary components like turn-on snubbers. Devices in series are required to reach higher voltage. High-frequency HV converter in two-level or three-level bridges running 20 kHz or higher in many emerging applications, like MVDC networks with high-frequency transformers and energy storage integration is hard to be built by silicon solutions. The emerging HV wide-bandgap (WBG) power semiconductors, e.g., 10 kV SiC MOSFETs offer higher blocking capability, faster and more efficient switching performances. This makes the high-frequency power conversion technology feasible for the MV area. To build a MV high-frequency power converter with high-power density, 10 kV SiC MOSFETs in series are required to reach >10 kV operation dc voltage as the single device rating is still limited by the semiconductor process and packaging capability. However, the knowledge of dynamic voltage sharing of high-speed HV SiC devices under high dv/dt rate and effective balancing methods are not fully explored. Both the voltage imbalance and the robust device voltage balancing control are not studied clearly in the existing literature. This dissertation evaluates the voltage imbalance of series-connected 10 kV SiC MOSFETs thoroughly. The parasitic capacitors connected with device terminals are found to be a unique factor for the voltage imbalance of series-connected SiC MOSFETs, which have a significant impact on the dv/dt of different devices based on the detailed analysis. The unbalanced dv/dt and the gate signal mismatch together result in the voltage imbalance of series-connected SiC MOSFETs and a set of new voltage balancing control methods are proposed. Passive capacitor compensation and closed-loop short pulse gate signal control are proposed to solve the voltage imbalance caused by the unbalanced dv/dt. Closed-loop gate delay time control is proposed to solve the voltage imbalance caused by the gate signal mismatch. Two gate driver prototypes are designed and verified for the proposed voltage balancing control methods. As the number of devices increases, the voltage balancing methods under the device-level will be complex and risky to coordinate. Therefore, the converter-level device voltage balancing methods are desired when over three devices are in stack. Therefore, this dissertation proposes to use the 3-level (3L) neutral-point-clamped (NPC) converter structure as a converter-level approach to simplify the voltage balancing control of series-connected SiC MOSFETs. A new modulation strategy is proposed to control the loss of clamping diodes, so compact MV SiC Schottky diodes can be selected to reduce the impact of extra components on the power density. Compared to the phase-leg with direct series-connected SiC MOSFETs, the phase-leg designed with the converter-level approach achieves similar power density, easier voltage balancing control, and better efficiency, which is attractive for both two and four devices in series connection. Finally, this dissertation studies the impact of series-connected 10 kV SiC MOSFETs on MV phase-leg volume reduction with the example of multi-level flying capacitor (FC) converters. The relation between the capacitances of FCs and the device voltage is studied and a new design procedure for FCs is developed to achieve minimum FC energy and regulate the maximum device voltage. With the design procedure, the total FC volumes of a 22 kV 5-level FC converter and a 22 kV 3-level FC converter with series-connected 10 kV SiC MOSFETs are calculated and compared. Series-connected 10 kV SiC MOSFETs are found to help significantly reduce the total FC volume (> 85 %). In summary, this dissertation demonstrates that the direct series connection of 10 kV SiC MOSFETs is a reliable solution for the MV converter design, and the converter-level approach is a better voltage balancing control method. This dissertation also presents a quantitative analysis of the volume reduction enabled by the series-connected 10 kV SiC MOSFETs in MV converter phase-leg design. / Doctor of Philosophy / Emerging industrial applications require medium voltage (MV) power converters. For existing MV converter solutions with Si IGBT, complex system structures are usually required, which affects the efficiency, power density, and cost of the system. For the design of MV converter, the recent 10 kV SiC MOSFET has the promising potential to improve efficiency and power density by adopting a simpler topology and fewer conversion stages. New design challenges also emerge with the new 10 kV SiC MOSFETs and one of them is the device voltage control during the operation. This dissertation mainly focuses on the voltage balancing control of series-connected 10 SiC MOSFETs, which is an attractive solution to build the MV converter phase-leg in a simple structure. Several voltage balance control methods are proposed and compared in this dissertation, which helps justify that the series-connected SiC MOSFET is a reliable approach for the MV converter design. In addition, this dissertation also analyzes the volume reduction enabled by the series-connected SiC MOSFETs with the example of a multi-level flying capacitor converter in dc-ac applications.

Distributed parameter systems (DPS) are systems defined on infinite dimensional spaces. This includes problems governed by partial differential equations (PDEs) and delay differential equations. In order to numerically implement a controller for a physical system we often first approximate the PDE and the PDE controller using some finite dimensional scheme. However, control design at this level will typically give rise to controllers that are inherently large-scale. This presents a challenge since we are interested in the design of robust, real-time controllers for physical systems. Therefore, a reduction in the size of the model and/or controller must take place at some point. Traditional methods to obtain lower order controllers involve reducing the model from that for the PDE, and then applying a standard control design technique. One such model reduction technique is balanced truncation. However, it has been argued that this type of method may have an inherent weakness since there is a loss of physical information from the high order, PDE approximating model prior to control design. In an attempt to capture characteristics of the PDE controller before the reduction step, alternative techniques have been introduced that can be thought of as controller reduction methods as opposed to model reduction methods. One such technique is LQG balanced truncation. Only recently has theory for LQG balanced truncation been developed in the infinite dimensional setting. In this work, we numerically investigate the viability of LQG balanced truncation as a suitable means for designing low order, robust controllers for distributed parameter systems. We accomplish this by applying both balanced reduction techniques, coupled with LQG, MinMax and central control designs for the low order controllers, to the cable mass, Klein-Gordon, and Euler-Bernoulli beam PDE systems. All numerical results include a comparison of controller performance and robustness properties of the closed loop systems. / Ph. D.

Multidisciplinary design optimization (MDO) for large-scale engineering problems poses many challenges (e.g., the design of an efficient concurrent paradigm for global optimization based on disciplinary analyses, expensive computations over vast data sets, etc.) This work focuses on the application of distributed schemes for massively parallel architectures to MDO problems, as a tool for reducing computation time and solving larger problems. The specific problem considered here is configuration optimization of a high speed civil transport (HSCT), and the efficient parallelization of the embedded paradigm for reasonable design space identification. Two distributed dynamic load balancing techniques (random polling and global round robin with message combining) and two necessary termination detection schemes (global task count and token passing) were implemented and evaluated in terms of effectiveness and scalability to large problem sizes and a thousand processors. The effect of certain parameters on execution time was also inspected. Empirical results demonstrated stable performance and effectiveness for all schemes, and the parametric study showed that the selected algorithmic parameters have a negligible effect on performance. / Master of Science

The focus of this research is the line assignment problem in printed circuit card assembly systems. The line assignment problem involves the allocation of circuit card types to an appropriate assembly line among a set of assembly lines with the objective of reducing the total assembly time. These circuit cards are to be assembled in a manufacturing facility, capable of simultaneously producing a wide variety of printed circuit cards in different production volumes. A set of component types is required for each printed circuit card. The objective is to assign the circuit cards to the assembly line such that the total assembly time, which includes the setup time as well as the processing time required for all card types in a set, is minimized. The focus of this research is to develop an algorithmic strategy for addressing this problem in electronics assembly. This problem involves considering several interrelated decision problems such as assigning printed circuit cards to assembly lines, grouping circuit cards into families to reduce the number of setups, and assigning component types to machines to balance workload. The line assignment models are formulated as large scale mixed integer programming problems and are solved using a branch-and-bound algorithm, supplemented by techniques for improving the solution time. The models and solution approaches are demonstrated using industry representative data sets and can serve as useful decision support tools for process planning engineers. / Master of Science

In the last two-decades data center networks have evolved to become a key element in improving levels of productivity and competitiveness for different types of organizations. Traditionally data center networks have been constructed with 3 layers of switches, Edge, Aggregation, and Core. Although this Three-Tier architecture has worked well in the past, it poses a number of challenges for current and future data centers. Data centers today have evolved to support dynamic resources such as virtual machines and storage volumes from any physical location within the data center. This has led to highly volatile and unpredictable traffic patterns. Also The emergence of "Big Data" applications that exchange large volumes of information have created large persistent flows that need to coexist with other traffic flows. The Three-Tier architecture and current routing schemes are no longer sufficient for achieving high bandwidth utilization. Data center networks should be built in a way where they can adequately support virtualization and cloud computing technologies. Data center networks should provide services such as, simplified provisioning, workload mobility, dynamic routing and load balancing, equidistant bandwidth and latency. As data center networks have evolved the Three-Tier architecture has proven to be a challenge not only in terms of complexity and cost, but it also falls short of supporting many new data center applications. In this work we propose OneSwitch: A switch architecture for the data center. OneSwitch is backward compatible with current Ethernet standards and uses an OpenFlow central controller, a Location Database, a DHCP Server, and a Routing Service to build an Ethernet fabric that appears as one switch to end devices. This allows the data center to use switches in scale-out topologies to support hosts in a plug and play manner as well as provide much needed services such as dynamic load balancing, intelligent routing, seamless mobility, equidistant bandwidth and latency. / PHD