A physics-based insulated gate bipolar transistor (IGBT) model has been successfully implemented into a widely available circuit simulation package, IG-Spice. Based on the semiconductor physics, the model accurately predicts the nonlinear junction capacitance variations, recombinations, and conductivity modulation of the power device. The procedure to incorporate the model into IG-Spice and various methods to ensure convergence are described. The IG-Spice IGBT model is presented, including all the physical effects which have been shown to be important in describing the device. Effectiveness of the model is shown by comparing the measured data for single device used in inductive load, and by comparing the static and dynamic current sharing of paralleled IGBTs. The simulated results are verified with experimental results. Accuracy is determined by the accuracy of the required parameters extracted. / Master of Science

The objective of this work is to investigate the performance of SiGe HBTs and scaled CMOS devices in extreme environments. In this work, the inverse mode operation of SiGe HBTs is investigated as a potential solution to the vulnerability of SiGe HBTs to single event effects. The performance limitations of SiGe HBTs operating in inverse mode are investigated through an examination of the effects of scaling on inverse mode performance and optimization schemes for inverse mode performance enhancements are discussed and demonstrated. In addition the performance of scaled MOSFETs, that constitute the digital backbone of any BiCMOS technology, is investigated under radiation exposure and cryogenic temperatures. Extreme environments and their effects on semiconductor devices are introduced in Chapter 1. The immunity of 90nm MOSFETs to total ionizing dose damage under proton radiation is demonstrated. Inverse mode operation of SiGe HBTs is introduced in Chapter 2 as a potential radiation hard solution by design. The effect of scaling on inverse mode performance of SiGe HBTs is investigated and the performance limitations in inverse mode are identified. Optimization schemes for improving inverse mode performance of SiGe HBTs are discussed in Chapter 3. Inverse mode performance enhancement is demonstrated experimentally in optimized device structures manufactured in a commercial third generation SiGe HBT BiCMOS platform. Further, a cascode device structure, the combines the radiation immunity of an inverse mode structure with the performance of a forward mode common emitter device is XIV discussed. Finally, idealized doping profiles for inverse mode performance enhancement is discussed through TCAD simulations. The cryogenic performance of inverse mode SiGe HBTs are discussed in Chapter 4. A novel base current behavior at cryogenic temperature is identified and its effect on the inverse mode performance is discussed. Matching performance of a 90nm bulk CMOS technology at cryogenic temperatures is investigated experimentally and through TCAD simulations in Chapter 5. The effect of various process parameters on the temperature sensitivity of threshold voltage mismatch is discussed. The potential increase of mismatch in subthreshold MOSFETs operating in cryogenic temperatures due to hot carrier effects is also investigated.

Thesis--Auburn University, 2009. / Abstract. Vita. Includes bibliographic references (p.64-66).

This thesis presents thermal and power loss models of a three phase IGBT voltage source inverter used in the design of the 625KW fuel cell and reformer demonstration which is a top priority for the Office of Naval Research. The ability to generate thermal simulations of systems and to accurately predict a system's response becomes essential in order to reduce the cost of design and production, increase reliability, quantify the accuracy of the estimated thermal impedance of an IGBT module, predict the maximum switching frequency without violating thermal limits, predict the time to shutdown on a loss of coolant casualty, and quantify the characteristics of the heat-sink needed to dissipate the heat under worst case conditions. In order to accomplish this, power loss and thermal models were created and simulated to represent a three phase IGBT voltage source inverter in the lab. The simulated power loss and thermal model data were compared against the experimental data of a three phase voltage source inverter set up in the Naval Postgraduate School power systems laboratory.

"Due to the high variation of critical device parameters inherent in integrated circuit manufacturing, modern integrated circuit designs have evolved to rely on the ratios of similar devices for their performance rather than on the absolute characteristics of any individual device. Today's high performance analog integrated circuits depend on the ability to make identical or matched devices. Circuits are designed using a tolerance based on the overall matching characteristics of their particular manufacturing process. Circuit designers also follow a general rule of thumb that larger devices offer better matching characteristics. This results in circuits that are over designed and circuit layouts that are generally larger than necessary. In this project we develop a model to predict the mismatch in a pair of NPN bipolar transistors. Precise prediction of device mismatch will result in more efficient circuit deigns, smaller circuit layouts and higher test yields, all of which lead to into more reliable and less expensive products."

A number of shortcomings were found after complete derivation of the temperature dependence of equations, and the expressions related to the Early effect in the present Gummel-Poon 2 model, as implemented in the TEKSPICE program. The formulation and application of improved model equations is presented, followed by a detailed comparison of the existing model with the one developed in this work.

The BICMOS technology which integrates the CMOS technology with bipolar technology has drawn considerable attention as an attractive VLSI technology because of the high speed performance and low power consumption of the BICMOS. However, continued down scaling of CMOS devices has caused increased concerns with problems such as latch up, hot carriers and short channel effect. Most of the above mentioned problems can be avoided by operating the CMOS at liquid-nitrogen temperature(LNT). At low-temperatures, the CMOS exhibits lower sub threshold leakage, higher carrier mobility (which yields improved speed performance), and a steeper logarithmic currentvoltage slope. On the other hand, the low-temperature operation of conventional silicon bipolar circuits has been generally dismissed as impractical because of the well known decrease in the current gain at low temperature. The present interest in integrated bipolarCMOS circuits, plus the prospect of increased reliability, lower wiring delay, and lower noise, has revised interest in low-temperature bipolar devices. In this context, it is therefore important to acquire accurate knowledge of the transistor properties at liquid nitrogen temperature. This can be done in two ways. One is through experimental lowtemperature measurements and the other by low-temperature device simulations. Existing room temperature numerical simulators are typically not useful for low temperature conditions. This is because the physical assumptions such as complete ionization, the parameter models and implementation methods for room temperature condition do not hold at low temperature. Therefore, we used BiLow - a steady state onedimensional Bipolar Low Temperature Simulator for the temperature range of 77K- 300K. This simulator, originally written in FORTRAN, was converted to C for the dual purpose of proper memory management and making further modifications easier. The focus of this research has been to model bandgap narrowing, incomplete ionization and Mott Transition at room and at low-temperature, evaluate the performance of the new BiLow and to derive conclusions on the BIT performance at LNT. It was observed that the bandgap narrowing was independent of temperature for the entire range of majority carrier concentration. The effect of Mott transition on the abrupt decrease in the electron concentration in emitter has been taken care of by smoothing out the concentration profile in the emitter thereby providing a continuity in the region of Mott transition. Both the current gain(~) and the frequency(ft) values obtained from simulating the two new profiles were found to be smaller than those obtained using the original BiLow simulator, as the doping in the base is higher and the device sizes were smaller. Most of the degradation in 13 and ft was found to occur below 150K. From the plots of the charge characteristics, we found that the total charge which is a strong function of temperature is more in the case of the profiles studied for this work than the total charge from the original BiLow simulator.

The function of a frequency multiplier is verbatim -- a frequency multiplier is a circuit that takes a signal of particular frequency at the input and produces harmonic multiples of the input signal's frequency at the output. Their use is widespread throughout history, primarily in the application of frequency synthesis. When implemented as a part of a large system, a chain of multipliers can be used to synthesize multiple reference signals from a single high-performance reference oscillator. Frequency multiplier designs use a variety of nonlinear devices and topologies to achieve excitation of harmonics. This thesis will focus on the design and analysis of single ended bipolar junction transistor frequency multipliers. This topology serves as a relatively simple design that lends itself to analysis of device parasitics and nonlinearities. In addition, design is done in the Very High Frequency (VHF) band of 30-300 MHz to allow for design and measurement freedoms. However, the design methodologies and theory can be frequency scaled as needed. The parasitics and nonlinearities of frequency multipliers are well explored on the output side of circuit design, but literature is lacking in analysis of the drive network. In order to explore device nonlinearities on the drive side of the circuit, this thesis implements novel nonlinear reflectometry systems in both simulations and real-world testing. The simulation nonlinear reflectometry consists of intelligently configured voltage sources, whereas directional couplers allow for real world nonlinear reflectometry measurements. These measurements allow for harmonically rich reflected waveforms to be accurately measured, allowing for waveform engineering to be performed at the drive network. Further, nonlinear reflectometry measurements can be used to explain how load- and source-pull obtained drive and load terminations are able to achieve performance increases.

In this work a new current-sweep stress methodology for quantitatively assessing the mixed-mode reliability (simultaneous application of high current and high voltage) of advanced SiGe HBTs is presented. This stress methodology allows one to quickly obtain the complete damage spectrum of a given device from a particular technology platform, enabling better understanding of the complex voltage, current, and temperature interdependence associated with electrical stress and burn-in of advanced transistors. We consistently observed three distinct regions of mixed-mode damage in SiGe HBTs, and find that hot carrier induced damage can be introduced into SiGe HBTs under surprisingly modest mixed-mode stress conditions. For more aggressively scaled silicon-germanium technology generations, a larger percentage of hot carriers generated in the collector-base junction are able to travel to and hence damage the EB spacer, leading to enhanced forward-mode base current leakage under stress. A new self-heating induced mixed-mode annealing effect was observed for the first time under fairly high voltage and current stress conditions, and a new damage mechanism was observed under very high voltage and current conditions. Finally, as an example of the utility of our stress methodology, we quantified the composite mixed-mode damage spectrum of a commercial third-generation (200 GHz) generation SiGe HBT. It is found that if devices are stressed with either voltage or current alone during burn-in, they can easily withstand extreme over-stress conditions. Unfortunately, devices were easily damaged when stressed with a combination of stress voltage and current, and this has significant implications for the device and circuit lifetime prediction under realistic mixed-signal operating conditions.

Originally presented as the author's thesis (Swiss Federal Institute of Technology), Diss. ETH No. 13547. / Summary in German and English. Includes bibliographical references.