This work investigates the fundamental device limits related to operational voltage constraints and linearity in state-of-the-art silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) in order to support the design of robust next-generation high-frequency transceivers. This objective requires a broad understanding of how much "usable" voltage exists compared to conventionally defined breakdown voltage specifications, so the role of avalanche-induced current-crowding (or "pinch-in") effects on transistor performance and reliability are carefully studied. Also, the effects of intermodulation distortion are examined at the transistor-level for new and better understanding of the limits and trade-offs associated with achieving enhanced dynamic range and linearity performance on existing and future SiGe HBT technology platforms. Based on these investigations, circuits designed for superior dynamic range performance are presented.

As Si-manufacturing compatible SiGe HBTs are making rapid in-roads into RF through mm-wave circuit applications, with performance levels steadily marching upward, the use of these devices under extreme environment conditions are being studied extensively. In this work, test structures of SiGe HBTs were designed and put into extremely low temperatures, and a new negative differential resistance effect and a novel collector current kink effect are investigated in the cryogenically-operated SiGe HBTs. Theory based on an enhanced positive feedback mechanism associated with heterojunction barrier effect at deep cryogenic temperatures is proposed. The accumulated charge induced by the barrier effect acts at low temperatures to enhance the total collector current, indirectly producing both phenomena. This theory is confirmed using calibrated 2-D DESSIS simulations over temperature. These unique cryogenic effects also have significant impact on the ac performance of SiGe HBTs operating at high-injection. Technology evolution plays an important role in determining the magnitude of the observed phenomena, and the scaling implications are addressed. Circuit implication is discussed.

Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2010. / ENGLISH ABSTRACT: Voltage regulation on distribution networks has so far been done by means of mechanical tap changers. However, these tap changers are plagued by high maintenance costs due to the arcing caused while switching, which degrades both the contacts and transformer oil. The major advances made during the last decade with regard to semiconductor technology have led to the development of high power IGBTs. These high power IGBTs are capable of conducting currents up to 1 000 A, while the voltage over the IGBT reaches well over 3 000 V. Using these high power IGBTs to design and build a solid-state tap changer allows the tap changer to regulate the output voltage with higher accuracy and speed. The supporting hardware is also discussed, while the design is verified by the use of simulations and practical measurements conducted on a scale-model of the IGBT-based solid-state tap changer. / AFRIKAANSE OPSOMMING: Spannings regulasie op distribusie netwerke word hedendaags verrig deur meganiese tap geskalde spanning reguleerders. Maar hierdie tap skakelaars word konstant beïnvloed deur oorvonking wat plaasvind tussen die kontakte wat hierdie kontakte beskadig en die transformator olie degradeer. Die laaste dekade het groot vordering getoon in halfgeleier navorsing wat gelei het tot die ontwikkeling van hoë drywing halfgeleiers. Die halfgeleiers of IGBTs kan strome so groot soos 1 000 A gelei terwyl die spanning oor die halfgeleier 3 000 V kan oorskry. Die gebruik van die hoë drywing halfgeleiers maak die pad oop vir die ontwerp en bou van ’n tap geskakelde reguleerder wat die uitree spanning akurater en vinniger kan reguleer. Die aanvullende hardeware is ook bespreek en die ontwerp is geverifieër deur middel van simulasies en deur praktiese metings wat geneem is op ’n skaal model van die hoogspanning spannings reguleerder.

by C.Y. Ho. / Thesis (M.Phil.)--Chinese University of Hong Kong, 1989. / Bibliography: leaves [147]-[148]

Hiu Yung Wong. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2001. / Includes bibliographical references (leaves 104-111). / Abstracts in English and Chinese. / Abstract --- p.i / Acknowledgments --- p.iii / List of Figures --- p.ix / List of Tables --- p.xiii / Chapter 1 --- Introduction --- p.1 / Chapter 1.1 --- Motivation and Objectives --- p.1 / Chapter 1.2 --- Contributions --- p.3 / Chapter 1.3 --- Organization of the Thesis --- p.4 / Chapter 2 --- Devices and Fabrication Processes --- p.5 / Chapter 2.1 --- Introduction --- p.5 / Chapter 2.2 --- BJTs --- p.6 / Chapter 2.2.1 --- Structure and Modeling of BJTs --- p.6 / Chapter 2.2.2 --- Standard BJT Process and BJT Characteristics --- p.7 / Chapter 2.3 --- MOSFETs and Complementary MOS (CMOS) --- p.8 / Chapter 2.3.1 --- Structure and Modeling of MOSFETs --- p.8 / Chapter 2.3.2 --- Standard n-well CMOS Process and MOSFETs Charac- teristics --- p.11 / Chapter 2.4 --- BiCMOS Technology --- p.13 / Chapter 2.5 --- Summary --- p.14 / Chapter 3 --- Matching Properties --- p.15 / Chapter 3.1 --- Introduction --- p.15 / Chapter 3.2 --- Importance of Matched Devices in IC Design --- p.15 / Chapter 3.2.1 --- What is Matching? --- p.15 / Chapter 3.2.2 --- Low-power Systems --- p.16 / Chapter 3.2.3 --- Device Size Downward Scaling --- p.16 / Chapter 3.2.4 --- Analog Circuits and Analog Computing --- p.17 / Chapter 3.3 --- Measurement of Mismatch --- p.18 / Chapter 3.3.1 --- Definitions and Statistics of Mismatch --- p.18 / Chapter 3.3.2 --- Types of Mismatches --- p.20 / Chapter 3.3.3 --- Matching Properties of MOSFETs --- p.23 / Chapter 3.3.4 --- Matching Properties of BJTs and CLBTs --- p.27 / Chapter 3.4 --- Summary --- p.30 / Chapter 4 --- CMOS Compatible Lateral Bipolar Transistors (CLBTs) --- p.31 / Chapter 4.1 --- Introduction --- p.31 / Chapter 4.2 --- Structure and Operation --- p.32 / Chapter 4.3 --- DC Model of CLBTs --- p.34 / Chapter 4.4 --- Residual Gate Effect in Accumulation --- p.35 / Chapter 4.5 --- Main Characteristics of CLBTs --- p.37 / Chapter 4.5.1 --- Low Early Voltage --- p.37 / Chapter 4.5.2 --- Low Lateral Current Gain at High Current Levels --- p.38 / Chapter 4.5.3 --- Other Issues --- p.39 / Chapter 4.6 --- Enhanced CLBTs with Cascode Circuit --- p.40 / Chapter 4.7 --- Applications --- p.41 / Chapter 4.8 --- Design and Layout of CLBTs --- p.42 / Chapter 4.9 --- Experimental Results of Single pnp CLBT； nMOSFET and pMOSFET --- p.44 / Chapter 4.9.1 --- CLBT Gains --- p.46 / Chapter 4.9.2 --- Gate Voltage Required for Pure Bipolar Action --- p.47 / Chapter 4.9.3 --- I ´ؤ V and Other Characteristics of Bare pnp CLBTs --- p.49 / Chapter 4.9.4 --- Transfer Characteristics of a Cascoded pnp CLBT --- p.50 / Chapter 4.9.5 --- Transfer Characteristics of an nMOSFET --- p.51 / Chapter 4.9.6 --- Transfer Characteristics of Cascoded and Bare CLBTs Operating as pMOSFETs --- p.52 / Chapter 4.10 --- Summary --- p.53 / Chapter 5 --- Experiments on Matching Properties --- p.54 / Chapter 5.1 --- Introduction --- p.54 / Chapter 5.2 --- Objectives --- p.55 / Chapter 5.3 --- Technology --- p.57 / Chapter 5.4 --- Design of Testing Arrays --- p.57 / Chapter 5.4.1 --- nMOSFET Array --- p.57 / Chapter 5.4.2 --- pnp CLBT Array --- p.59 / Chapter 5.5 --- Design of Input and Output Pads (I/O Pads) --- p.62 / Chapter 5.6 --- Shift Register --- p.62 / Chapter 5.7 --- Experimental Equipment --- p.63 / Chapter 5.8 --- Experimental Setup for Matching Properties Measurements --- p.65 / Chapter 5.8.1 --- Setup for Measuring the Mismatches of the Devices --- p.65 / Chapter 5.8.2 --- Testing Procedures --- p.68 / Chapter 5.8.3 --- Data Analysis --- p.68 / Chapter 5.9 --- Matching Properties --- p.69 / Chapter 5.9.1 --- Matching Properties of nMOSFETs --- p.69 / Chapter 5.9.2 --- Matching Properties of CLBTs --- p.71 / Chapter 5.9.3 --- Matching Properties of pMOSFETs --- p.73 / Chapter 5.9.4 --- "Comments on the Matching Properties of CLBT, nMOSFET, and pMOSFET" --- p.76 / Chapter 5.9.5 --- "Mismatch in CLBT, nMOSFET, and pMOSFET Cur- rent Mirrors" --- p.77 / Chapter 5.10 --- Summary --- p.79 / Chapter 6 --- Conclusion --- p.80 / Chapter A --- Floating Gate Technology --- p.82 / Chapter A.1 --- Floating Gate --- p.82 / Chapter A.2 --- Tunnelling --- p.83 / Chapter A.3 --- Hot Electron Effect --- p.85 / Chapter A.4 --- Summary --- p.86 / Chapter B --- A Trimmable Transconductance Amplifier --- p.87 / Chapter B.1 --- Introduction --- p.87 / Chapter B.2 --- Trimmable Transconductance Amplifier using Floating Gate Com- patible Lateral Bipolar Transistors (FG-CLBTs) --- p.87 / Chapter B.2.1 --- Residual Gate Effect and Collector Current Modulation --- p.89 / Chapter B.2.2 --- Floating Gate CLBTs --- p.92 / Chapter B.2.3 --- Electron Tunnelling --- p.93 / Chapter B.2.4 --- Hot Electron Injection --- p.94 / Chapter B.2.5 --- Experimental Results of the OTA --- p.94 / Chapter B.2.6 --- Experimental Results of the FGOTA --- p.96 / Chapter B.3 --- Summary --- p.97 / Chapter C --- AMI-ABN 1.5μm n-well Process Parameters (First Batch) --- p.98 / Chapter D --- AMI-ABN 1.5μm n-well Process Parameters (Second Batch) --- p.101 / Bibliography --- p.104

Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1982. / MICROFICHE COPY AVAILABLE IN ARCHIVES AND ENGINEERING. / Vita. / Includes bibliographical references. / by Max Wolff Hauser. / M.S.

First, the concepts of reflection coefficients, s-parameters, Smith chart, noise figure, and available power gain will be introduced. This lays out the foundation for the presentation of techniques on measuring noise figure and gain of high speed bipolar junction transistors. Noise sources in a bipolar junction transistor and an equivalent circuit including these noise sources will be presented. The process of determining the noise parameters of a transistor will also be discussed. A Pascal program and several TEKSPICE scripts are developed to calculate the stability, available power gain, and noise figure circles. Finally, these circles are plotted on a Smith chart to give a clear view of how a transistor will perform due to a change in source impedances.

No description available.

A study of deep levels of the emitter region of a heterojunction bipolar transistor is investigated using deep level transient spectroscopy (DLTS), deep level admittance spectroscopy (DLAS), thermally stimulated capacitance (TSCAP), and capacitance-voltage (C-V) profiling. The DX center, with an activation energy of 0.45 eV, is the only deep level detected. By varying the DLTS rate window and filling pulse widths, DX is found to be comprise of two closely spaced DX centers, denoted DX1 and DX2. A positive peak observed in the DLTS spectra is attributed to electron capture, not minority carrier emission, and, thus, is an experimental artifact. Finally, the reduction of current gain (β) at low collector current and the effect of the DX center on the switching characteristics of HBTs are briefly discussed. / Graduation date: 1993

Transistor mismatch is a crucial design issue in high precision analog circuits, and is investigated here for the first time in SiGe HBTs. The goal of this work is to study the effects of mismatch under extreme conditions including radiation, high temperature, and low temperature. One portion of this work reports collector current mismatch data as a function of emitter geometry both before and after 63 MeV proton exposure for first-generation SiGe HBTs with a peak cut-off frequency of 60 GHz. However, minimal changes in device-to-device mismatch after radiation exposure were experienced. Another part of the study involved measuring similar devices at different temperatures ranging from 298K to 377K. As a general trend, it was observed that device-to-device mismatch improved with increasing temperature.