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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
11

Design and Implementation of a Cache Generator

Lin, Shih-Yun 26 July 2005 (has links)
As the complexity of System-on-a-Chip (SoC) designs increases, embedded memory components gradually occupy a significant portion of the total area cost, and the reusable memory Intellectual Property (IP) design becomes a critical issue. In this thesis, an automatic cache generator is developed which can be easily integrated into the current cell-based design flow. The generated cache contains both hard IP and soft IP. The storage array circuits are implemented as hard IP to reduce the area cost. The cache control unit is realized as soft IP. The hard IP of the core memory circuits mainly store data and tag information. The implementations of tag arrays can be divided into two categories: RAM-tag design and CAM (Content Addressable Memory)-tag design. We adopt the CAM-tag style in our cache design because CAM cells have the functions of storage as well as data-matching, and thus can be easily used to realize the tag function in cache. The soft IP of cache controller implements the different writing strategies and block replacement methods. The input parameters of the cache generator include cache size, block size, information on set-associativity, writing strategy, replacement methods, etc. The output of the cache generator contains the RTL code for the soft IP and other necessary Models for the hard IP so that the generated cache can be mixed with other pure cell-based design modules during synthesis and placement-and-routing.
12

Caching Strategies for Dynamic Source Routing in Mobile Ad Hoc Networks

Chan, Chi-Chen 13 February 2007 (has links)
The Dynamic Source Routing (DSR) protocol usually utilizes route caching to reduce the routing overhead and route discovery latency. For caches to be effective, the protocol needs to adapt to the frequent topology changes. In this paper, we propose two mechanisms to improve cache correctness and route stability. The first is the RERR-Enhance mechanism in which a broken link message will be sent to all nodes that had cached the broken link. The second mechanism is the hierarchical link cache structure accompanied with a link stability measurement. The cache in each node falls into two tiers: the primary cache and the secondary cache. The node selects a route from the primary cache first, based on link stability, to provide stable transmission. The proposed mechanism reduces at least 13% of the broken link messages; it also reduces routing overhead and end-to-end delay, compared to DSR with path caches and with Link-MaxLife, an adaptive timeout mechanism for link caches.
13

Client-side data caching in mobile computing environments /

Xu, Jianliang. January 2002 (has links)
Thesis (Ph. D.)--Hong Kong University of Science and Technology, 2002. / Includes bibliographical references (leaves 146-158). Also available in electronic version. Access restricted to campus users.
14

Cache performance analysis of algorithms /

Fix, James D., January 2002 (has links)
Thesis (Ph. D.)--University of Washington, 2002. / Vita. Includes bibliographical references (p. 103-109).
15

Extended data cache prefetching using a reference prediction table /

Kim, Donglok. January 1997 (has links)
Thesis (Ph. D.)--University of Washington, 1997. / Vita. Includes bibliographical references (leaves [76]-77).
16

Cache miss analysis of Walsh-Hadamard Transform algorithms /

Furis, Mihai Alexandru. Johnson, Jeremy. January 2003 (has links)
Thesis (M.S.)--Drexel University, 2003. / Includes abstract. Includes bibliographical references (leaves 64-65).
17

Volume lease: a scalable cache consistency framework

Yin, Jian 28 August 2008 (has links)
Not available / text
18

Improving cache utilisation

Srinivasan, James Richard January 2011 (has links)
No description available.
19

Kompiuterių hierarchinės atminties sistemos tyrimas / The study of computer hierarchical memory

Rimavičius, Vidmantas 23 May 2005 (has links)
The operating speed of computers tends to increase significantly, however, this process is not simple. It can be explained, that operating speed depends on how fast the computer facilities are as well as their balance. Modern processors can perform operations within several cycles meanwhile the selection time of big size main memory reaches tens and hundreds of cycles. Although the static memory able to operate at speed equal or close to processor’s operating speed exists, it’s using for main memory is expensive. Problem is solved by installing the small size cache between processor and main memory. Relatively small but very fast memory called cache takes a specific position in modern computer memories system. Cache is a highest level of hierarchical memories system. Cache simulator for exploring of cache behaviour was developed. Cache’s influence on computer efficiency from both theoretical and practical point of view, the latter to be supported with simulation results, is analysed in this master thesis. Comparing the theoretical and test results the influence of different factors to the operation of hierarchical memories system is evaluated. The results of cache simulation show that the operation of hierarchical memory system is impacted by functioning of cache levels, the frequence of accesses to the memory, the hit rate (or miss rate), the cache organisation, line replacement algorithm, cache size, cache line size as well as specific properties of program executed.
20

Volume lease a scalable cache consistency framework /

Yin, Jian. Dahlin, Mike, Alvisi, Lorenzo, January 2003 (has links) (PDF)
Thesis (Ph. D.)--University of Texas at Austin, 2003. / Supervisor: Mike Dahlin and Lorenzo Alvisi. Vita. Includes bibliographical references. Available also from UMI Company.

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