The smart dust concept is a fairly recent phenomenon to engineering. It assumes monitoring of a real natural environment in which motes or smart dust machines swarm in collective and coordinate information among themselves and/or to a backend control platform. In analog mixed signal field work on such devices is gaining momentum such that it is conceived to be one of the emerging fields in technology, and work was only possible once the technology for fabrication touched the nanoscale regions. Smart dust network involves remote devices connected in a hive sensing burst type datum signals from the environment and relaying information amongst themselves in an energy efficient manner to coordinate an appropriate response to a detected stimulus. The project presumed a RF based communication strategy for coordination amongst the devices through a wireless medium. That is less susceptible to stringent requirements of LOS and a base band processing system that comprised of an environment sensor, an AFE module, an ADC, a DSP and a DAC. Essentially a 10 bit, 2 Mega Hertz MHz pipelined ADC implemented in a STM 65nm technology. The ADC benefits the smart dust device in allowing it to process data in an energy efficient way and also focusing on reduced complexity as itsdesign feature. While it differs in the other ADC of the system by operating at a higher frequency and assuming a different design philosophy assuming a coherent system sensitive to a clock. The thesis work assumes that various features ofenergy harvesting, regulation and power management present in the smart dustmote would enable the system to contain such a diverse ADC. The ADCs output digital datum would be compatible to the rest of the design modules consisting mainly of DSP sections. The ADC novelty is based on the fact that it removes the necessity of employing a high power consuming OpAmp whose design parameters become more complex as technology scales to the nanoscale era and further down. A systematic, bottom up, test driven approach to design is utilized and various behaviours of the system are captured in Cadence design environment with verilogto layout models and MATLAB and Simulink models.

This thesis presents the design and fabrication of coplanar waveguide to microstrip transitions and planar spiral inductors, and the design of metal-insulator-metal capacitors, a planar band-pass, and a low-pass filter structures as an application for the inductors and capacitors using the RF MEMS technology. This thesis also includes a packaging method for RF MEMS devices with the use of benzocyclobutene as bonding material. The transition structures are formed by four different methods between coplanar waveguide end and microstrip end, and they are analyzed in 1-20 GHz. Very low loss transitions are obtained by maintaining constant characteristic impedance which is the same as the port impedance through the transition structures. The planar inductors are formed by square microstrip spirals on a glass substrate. Using the self-inductance propery of a conductive strip and the mutual inductance between two conductor strips in a proper arrangement, the inductance value of each structure is defined. Inductors from 0.7 nH up to 20 nH have been designed and fabricated. The metal-insulator-metal capacitors are formed by two coplanar waveguide structures. In the intersection, one end of a coplanar waveguide is placed on top of the end of the other coplanar waveguide with a dielectric layer in between. Using the theory of parallel plate capacitors, the capacitance of each structure is adjusted by the dimensions of the coplanar waveguides, which obviously adjust the area of intersection. Capacitors from 0.3 pF up to 9.8 pF have been designed. A low-pass filter and a band-pass filter are designed using the capacitors and inductors developed in this thesis. In addition to lumped elements, the interconnecting transmission lines, junctions and input-output lines are added to filter topologies. The RF MEMS packaging is realized on a coplanar waveguide structure which stands on a silicon wafer and encapsulated by a silicon wafer. The capping chip stands on the BCB outer ring which promotes adhesion and provides semi hermeticity. Keywords: Transition between transmission lines, planar spiral inductor, metal-insulator-metal capacitor, RF MEMS packaging, surface micromachining.

In this research work, the performance of a C-type, 2nd harmonic power filter is optimized by the use of a thyristor switched damping resistor. In the design of conventional C-type, 2nd harmonic filters / the resistance of permanently connected damping resistor is to be optimized for minimization of voltage stresses on filter elements arising from switchings in transient state and for maximization of filtering effectiveness in the steady-state. Transformer inrush current during energization of power transformers and connection of filter bank to the supply are the major causes of voltage stresses arising on filter elements in transient state. These can be minimized by designing a highly damped C-type filter (low damping resistor) at the expense of inadequate filtering performance and high losses in the steady-state. On the other hand, higher damping resistance (high quality factor) is to be chosen in the design of C-type filter for satisfactory filtering of 2nd harmonic current component at the expense of higher voltage rating for capacitor bank and hence a more costly filter bank design. This drawback of conventional C-type 2nd harmonic filter circuit can be eliminated by subdividing damping resistor into two parallel parts / one is permanently connected while the other is connected to and disconnected from the circuit by back-to-back connected thyristor assemblies. The use of light triggered thyristors provides isolation between power stage and control circuit, and hence allows outdoor installation.

This research work deals with the analysis, design and implementation of thyristor switched plain capacitor banks and thyristor switched shunt filter banks. Performances of various thyristor switched capacitor (TSC) topologies are also investigated by simulations. The theoretical findings have been verified by carrying out experimental work on two prototypes implemented within the scope of this research work, one is a wye-connected laboratory prototype and the other is a delta-connected application prototype integrated to some of the SVCs existing in Turkish Coal Enterprise s Plants. The advantages of back-to-back connected thyristor switches over conventional electromechanical contactors are also made clear by conducting an intensive experimental work in the laboratory. A good correlation have been obtained between theoretical and experimental results.

AC/DC adapters mostly employ two-stage topology: Power Factor Correction (PFC) pre-regulation stage followed by an isolated DC/DC converter stage. Low power AC/DC adapters require a small size to be competitive. Among their components, the bulk DC-link capacitor is one of the largest because it should keep the output voltage with low ripple. Also, the size of this capacitor is penalized due to the universal line voltage application. Synchronization through employing leading edge modulation for the first PFC stage and trailing edge modulation for the second DC/DC converter stage can significantly reduce the ripple current and ripple voltage of the DC-link capacitor. Thus, a smaller DC-link capacitance can be used, lowering the cost and size of the AC/DC adapter. Benefits of the synchronous switching scheme were already demonstrated experimentally. However, no mathematical analysis was presented. In this thesis, detailed mathematical analyses in per-unit quantity are given to facilitate the calculation of the DC-link capacitor ripple current reduction with Leading/Trailing Edge Modulation strategies. One of the limitations of leading/trailing edge modulation is that the switching frequencies of the two stages need to be equal to achieve the best reduction of the DC-link capacitor ripple current. The DC-link capacitor ripple current will become larger if the switching frequency of the DC/DC converter is larger than that of the PFC pre-regulator, which blocks us to employ higher frequency for isolated DC/DC converter to reduce its transformer size. This thesis proposed a new Leading/Trailing Edge Modulation strategy to further reduce the DC-link bulk capacitor ripple current when switching frequency of DC/DC converter stage is twice the switching frequency of PFC stage. This proposed pulse width modulation scheme was verified by simulation. Experimental results obtained through digital control based on FPGA are also presented in this thesis.

<p>Series compensation of transmission lines is an effectiveand cheap method of improving the power transmission systemperformance. Series capacitors virtually reduces the length ofthe line making it easier to keep all parts of the power systemrunning in synchronism and to maintain a constant voltage levelthroughout the system. In Sweden this technology has been inuse since almost 50 years.</p><p>The possibility to improve the performance of the ACtransmission system utilizing power electronic equipment hasbeen discussed a lot since about ten years. Some newsemiconductor based concepts have been developed beside thesince long established HVDC and SVC technologies. The ThyristorControlled Series Capacitor (TCSC) is one such concept. Byvarying the inserted reactance an immediate and well-definedimpact on the active power flow in the transmission line isobtained. Several potential applications, specifically poweroscillation damping, benefit from this capability. The conceptimplied the requirement to design a semiconductor valve, whichcan be inserted directly in the high-voltage power circuit.This certainly presented a technical challenge but thestraightforward approach appeared to be a cost-effectivealternative with small losses.</p><p>It was also realized that the TCSC exhibits quite differentbehaviour with respect to subsynchronous frequency componentsin the line current as compared to the fixed series capacitorbank. This was a very interesting aspect as the risk ofsubsynchronous resonance (SSR), which just involves such linecurrent components, has hampered the use of series compensationin power systems using thermal generating plants.</p><p>The thesis deals with the modelling and control aspects ofTCSC. A simplifying concept, the equivalent, instantaneousvoltage reversal, is introduced to represent the action of thethyristor controlled inductive branch, which is connected inparallel with the series capacitor bank in the TCSC. The idealvoltage reversal is used in the thesis in order to describe andexplain the TCSC dynamics, to investigate its apparentimpedance at various frequencies, as a platform forsynthesizing the boost control system and as the base elementin deriving a linear, small-signal dynamical model of thethree-phase TCSC. Quantitative Feedback Theory (QFT) then hasbeen applied to the TCSC model in order to tune its boostregulator taking into account the typical variation ofparameters that exists in a power system. The impact of theboost control system with respect to damping of SSR is finallybeing briefly looked at.</p><p><b>Keywords:</b>Thyristor Controlled Series Capacitor, TCSC,FACTS, reactive power compensation, boost control, phasorestimation, Quantitative Feedback Theory, subsynchronousresonance, SSR.</p>

<p>The sigma-delta techniques for analog-to-digital conversion have for long been utilized when high precision is needed. Despite the fact that these have been realized by a numerous of different structures, the theory of how to construct a sigma-delta ADC is not very extensive.</p><p>This thesis will assume that an SFG description of the CRFB sigma-delta modulator has been designed and presents a structured method to obtain a circuit realization of the integrators in a specific modulator.</p><p>The first activity is to scale the inputs to each integrator in order to make sure that the produced outputs of each integrator is within the output-range of the OTA which is used. The next thing that is presented is an algorithmic way of descending from the SFG design of the modulator down to a switched-capacitor implementation of the system.</p><p>To be able to continue with the circuit realization, one needs to do a rigorous noise analysis of the modulator, which gives the sizes of the different capacitors in the SC-circuits. The last topic of this thesis is a method to obtain the specifications of the OTA in each integrator.</p>

The objective of the proposed research is to advance the power efficiency of wireless neural stimulating systems in inductively powered implantable medical devices (IMD). Several innovative system- and circuit-level techniques are proposed towards the development of power-management circuits and wireless neural stimulating systems with inductive power transmission to improve the overall stimulation power efficiency. Neural stimulating IMDs have been proven as effective therapies to alleviate neurological diseases, while requiring high power and performance for more efficacious treatments. Therefore, power-management circuits and neural stimulators in IMDs should have high power efficiencies to operate with smaller received power from a larger distance. Neural stimulating systems are also required to have high stimulation efficacy for activating the target tissue with a minimum amount of energy, while ensuring charge-balanced stimulation. These features provide several advantages such as a long battery life in an external power transmitter, extended-range inductive power transfer, efficacious and safe stimulation, and less tissue damage from overheating. The proposed research presents several approaches to design and implement the power-efficient wireless neural stimulating IMDs: 1) optimized power-management circuits for inductively powered biomedical microsystems, 2) a power-efficient neural stimulating system with adaptive supply control, and 3) a wireless switched-capacitor stimulation (SCS) system, which is a combination structure of the power-management circuits and neural stimulator, to maximize both stimulator efficiency (before electrodes) and stimulus efficacy (after electrodes).

The sigma-delta techniques for analog-to-digital conversion have for long been utilized when high precision is needed. Despite the fact that these have been realized by a numerous of different structures, the theory of how to construct a sigma-delta ADC is not very extensive. This thesis will assume that an SFG description of the CRFB sigma-delta modulator has been designed and presents a structured method to obtain a circuit realization of the integrators in a specific modulator. The first activity is to scale the inputs to each integrator in order to make sure that the produced outputs of each integrator is within the output-range of the OTA which is used. The next thing that is presented is an algorithmic way of descending from the SFG design of the modulator down to a switched-capacitor implementation of the system. To be able to continue with the circuit realization, one needs to do a rigorous noise analysis of the modulator, which gives the sizes of the different capacitors in the SC-circuits. The last topic of this thesis is a method to obtain the specifications of the OTA in each integrator.

The constant strive for improvement of digital video capturing speeds together with power efficiency increase, has lead to tremendous research activities in the image sensor readout field during the past decade. The improvement of lithography and solid-state technologies provide the possibility of manufacturing higher resolution image sensors. A double resolution size-up, leads to a quadruple readout speed requirement, if the same capturing frame rate is to be maintained. The speed requirements of conventional serial readout techniques follow the same curve and are becoming more challenging to design, thus employing parallelism in the readout schemes appears to be inevitable for relaxing the analog readout circuits and keeping the same capturing speeds. This transfer however imposes additional demands to parallel ADC designs, mainly related to achievable accuracy, area and power. In this work a 12-bit Cyclic ADC (CADC) aimed for column-parallel readout implementation in CMOS image sensors is presented. The aim of the conducted study is to cover multiple CADC sub-component architectures and provide an analysis onto the latter to a mid-level of depth. A few various Multiplying DAC (MDAC) structures have been re-examined and a preliminary redundant signed-digit CADC design based on a 1.5-bit modified flip-over MDAC has been conducted. Three comparator architectures have been explored and a dynamic interpolative Sub-ADC is presented. Finally, some weak spots degrading the performance of the carried-out design have been analyzed. As an architectural improvement possibility two MDAC capacitor mismatch error reduction techniques have been presented.