Global ETD Search

1	Adaptive TDC : Implementation and Evaluation of an FPGA Andersson Holmström, Simon January 2015 (has links) Time to digital converter (TDC) is a digital unit that measures the time interval between two events.This is useful to determine the characteristics and patterns of a signal or an event. In this thesis ahybrid TDC is presented consisting of a tapped delay line and a clock counter principle. The TDC is used to measure the time between received data in a QKD application. If the measuredtime does not exceed a certain value then data had been sent without any interception. It is alsopossible to use TDCs in other fields such as laser-ranging and time-of-flight applications. The TDC consists of two carry chains, an encoder, a FIFO and a counter for each channel, anAXI-module and a control unit to generate command signals to all channels that are implemented.The time is measured by sampling the signal that has propagated through the carry chain and from thissample encode the propagation length. In this thesis a TDC is implemented that has a 10 ns dead time and a resolution below 28 psin a four channel mode. The propagation variation is approximately two percent of the total valueduring testing. For the implementation an FPGA-board with a Zynq XC7Z020 SoC is used withSystemVerilog that is a hardware describing language (HDL). TDC Carry-chain FPGA Zynq Delay
2	Methods for Reverse Engineering Word-Level Models from Look-Up Table Netlists Narayanan, Ram Venkat January 2022 (has links) No description available. Computer Engineering FPGA reverse engineering Gate-levell netlist reverse engineering Hardware security Carry-chain
3	A 1.8 ps Time-to-Digital Converter (TDC) Implemented in a 20 nm Field-Programmable Gate Array (FPGA) Using a Ones-Counter Encoding Scheme with Embedded Bin-Width Calibrations and Temperature Correction Sven, Engström January 2020 (has links) This thesis investigates the use of field-programmable gate arrays (FPGAs) to implement a time-to-digital converter (TDC) with on-chip calibration and temperature correction.Using carry-chains on the Xilinx Kintex UltraScale architecture to create a tapped delay line (TDL) has previously been proven to give good time resolution.This project improves the resolution further by using a bit-counter to handle bubbles in the TDL without removing any taps.The bit counter also adds the possibility of using a wave-union approach previously dismissed as unusable on this architecture.The final implementation achieves an RMS resolution of 1.8 ps. time-to-digital time-to-digital converter TDC 1.8 ps field-programmable gate array FPGA 20 nm Xilinx Kintex UltraScale tapped delay line TDL taps carry-chain ones-counter bit-counter bubbles wave-union embedded temperature correction Annan elektroteknik och elektronik

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