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1	A 1.8 ps Time-to-Digital Converter (TDC) Implemented in a 20 nm Field-Programmable Gate Array (FPGA) Using a Ones-Counter Encoding Scheme with Embedded Bin-Width Calibrations and Temperature Correction Sven, Engström January 2020 (has links) This thesis investigates the use of field-programmable gate arrays (FPGAs) to implement a time-to-digital converter (TDC) with on-chip calibration and temperature correction.Using carry-chains on the Xilinx Kintex UltraScale architecture to create a tapped delay line (TDL) has previously been proven to give good time resolution.This project improves the resolution further by using a bit-counter to handle bubbles in the TDL without removing any taps.The bit counter also adds the possibility of using a wave-union approach previously dismissed as unusable on this architecture.The final implementation achieves an RMS resolution of 1.8 ps. time-to-digital time-to-digital converter TDC 1.8 ps field-programmable gate array FPGA 20 nm Xilinx Kintex UltraScale tapped delay line TDL taps carry-chain ones-counter bit-counter bubbles wave-union embedded temperature correction Annan elektroteknik och elektronik