À mesure que les technologies de l'information (IT) continuent de croître, les dispositifs mémoires doivent évoluer pour répondre aux exigences du marché informatique. De nos jours, de nouvelles technologies émergent et entrent sur le marché. La mémoire Resistive Random Access Memory (RRAM) fait partie de ces dispositifs émergents et offre de grands avantages en termes de consommation d'énergie, de performances, de densité et la possibilité d'être intégrés en back-end. Cependant, pour être compétitif, certains problèmes doivent encore être surmontés en particulier en ce qui concerne la variabilité, la fiabilité et la stabilité thermique de la technologie. Leur place sur le marché des mémoires est encore indéfinie. En outre, comme le principe de fonctionnement des RRAM dépend des matériaux utilisés et doit être observé à la résolution nanométrique, la compréhension du mécanisme de commutation est encore difficile. Cette thèse propose une analyse du principe de fonctionnement microscopique des CBRAM à base d'oxyde basé sur des résultats de caractérisation électrique et de simulation atomistique. Une interdépendance entre les performances électriques des RRAM et certains paramètres matériaux est étudiée, indiquant de nouveaux paramètres à prendre en compte pour atteindre les spécifications d'une application donnée. / As Information Technologies (IT) are still growing, memory devices need to evolve to answer IT market demands. Nowadays, new technologies are emerging and are entering the market. Resistive Random Access Memory (RRAM) are part of these emerging devices and offer great advantages in terms of power consumption, performances, density and the possibility to be integrated in the back end of line. However, to be competitive, some roadblocks still have to be overcome especially regarding technology variability, reliability and thermal stability. Their place on memory market is then still undefined. Moreover, as RRAM working principle depends on stack materials and has to be observed at nanometer resolution, switching mechanism understanding is still challenging. This thesis proposes an analysis of oxide-based CBRAM microscopic working principle based on electrical characterization results and atomistic simulation. Then, an interdependence between RRAM electrical performances as well as material parameters is studied to point out new parameters that can be taken into account to target specific memory applications.

abstract: There is an ever growing need for larger memories which are reliable and fast. New technologies to implement non-volatile memories which are large, fast, compact and cost-efficient are being studied extensively. One of the most promising technologies being developed is the resistive RAM (ReRAM). In ReRAM the resistance of the device varies with the voltage applied across it. Programmable metallization cells (PMC) is one of the devices belonging to this category of non-volatile memories. In order to advance the development of these devices, there is a need to develop simulation models which replicate the behavior of these devices in circuits. In this thesis, a verilogA model for the PMC has been developed. The behavior of the model has been tested using DC and transient simulations. Experimental data obtained from testing PMC devices fabricated at Arizona State University have been compared to results obtained from simulation. A basic memory cell known as the 1T 1R cell built using the PMC has also been simulated and verified. These memory cells have the potential to be building blocks of large scale memories. I believe that the verilogA model developed in this thesis will prove to be a powerful tool for researchers and circuit developers looking to develop non-volatile memories using alternative technologies. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2014

Le marché de l’électronique flexible devrait atteindre un chiffre d’affaire de plus de 10 milliards de dollars à l’horizon 2020. La réalisation de circuits dotés de flexibilité mécanique accompagnera l’essor de nouvelles applications liées à l’internet des objets ou à l’électronique grande surface. Après la logique, la mémoire est un organe fondamental de tout système électronique. Dans cette thèse, nous nous sommes intéressés au développement de mémoires non-volatiles de type CBRAM (Conductive Bridge Random Acces Memory) pour les applications électroniques flexibles. Ces mémoires possèdent une structure MEM (Métal-Électrolyte-Métal) et font partie des mémoires non volatiles émergentes de type ReRAM (Resistive RAM). L’effet mémoire est basé sur une commutation de résistance due à des phénomènes d’oxydo-réduction et de migration ionique aboutissant à la formation/dissolution d’un filament conducteur dans l’électrolyte solide. La possibilité d’utiliser des verres de chalcogénures ou encore des polymères comme électrolytes solide offre à ces mémoires un avenir prometteur pour les applications flexibles. Après avoir passé en revue les différents matériaux exploités pour la réalisation de CBRAM, nous exposerons des travaux concernant la fabrication et la caractérisation de mémoires basées sur des électrolytes de GeS$_x$ et de Ge$_X$Sb$_Y$Te$_Z$ sur substrats de silicium. Les caractéristiques I-V obtenues (phénomènes de set et reset) sont ensuite confrontées à des simulations réalisées à l’aide d’un modèle électro-thermique qui considère le courant ionique comme facteur limitant. La dernière partie de ce travail est quant à elle dédiée au développement de mémoires flexibles. / Flexible electronics market revenue is expected to exceed $10B by 2020. Duento their mechanical flexibility, flexible circuits will enable numerous developmentsnin various fields from internet-of-things applications to large area electronics. Besides logic devices, memory is the second fundamental component of any electronic system. During this thesis, we aimed at developing nonvolatile memories referred as CBRAM (Conductive-Bridge Random Access Memories) for flexible electronics applications. These devices consist in a simple Metal-Electrolyte-Metal structure. The memory effect relies on resistance switching due to the formation/dissolution of a metallic conductive filament within a solid electrolyte. The use of chalcogenide glasses or polymers layers as solid-electrolytes offers many opportunities for future for flexible applications. In a first part, memory devices based on of GeS$_x$ and de Ge$_X$Sb$_Y$Te$_Z$ solid electrolytes on silicon substrates we fabricated and electrically tested. Experimental results were then confronted to an electro-thermal model, based on ionic current, developed during this thesis. The final chapter of this manuscript is devoted to the development of flexible memories.

Actuellement, l'étude et le développement d'oxydes à commutation de résistance pour des dispositifs mémoires (Resistive RAM, ou ReRAM) constituent un domaine d'activité intense sur le plan international. Les ReRAMs sont des structures MIM (Métal-Isolant-Métal) dont la résistance peut être modulée par l’application d’une tension. A ce jour, les mécanismes qui régissent la transition de résistance dans les dispositfs ReRAM sont toujours l’objet de débats. Le travail développé dans cette thèse représente une contribution au développement des mémoires ReRAM à base de HfO2. Nous nous intéressons plus particulièrement aux ReRAMs « à pont conducteur » (Conducting Bridge RAM, ou CBRAM) pour lesquelles la transition de résistance est provoquée par la diffusion du métal d’anode. Nous cherchons à améliorer la compréhension des phénomènes qui contrôlent le passage d’un état isolant à un état conducteur. Dans ce cadre, notre travail se focalise sur l’influence des métaux d'électrodes. Le rôle de l’anode et de la cathode sont précisés. Un modèle qualitatif est présenté permettant d’expliquer la commutation de résistance. Nous discutons également des mécanismes de conduction dans l’état de faible résistance. Enfin, l’impact de la structure de l’oxyde est étudié. / The Resistive Random Access Memory (ReRAM) technology is attracting growing interest as a potential candidate for the next generation of nonvolatile memories. ReRAMs are MIM (Metal-Insulator-Metal) devices whose resistance can be tuned by voltage bias. Today the physical mechanisms at the origin of resistance switching are not yet fully understood and are still under debate. In the present work, we are interested in HfO2-based ReRAMs, with a focus on Conducting Bridge RAM (CBRAM) devices in which resistance transition is ascribed to anode metal diffusion. Our goal is to better identify phenomena which govern the high to low resistance transition. In this context, we study the impact of different metal electrodes. The role played by the anode and the cathode is elucidated. A qualitative model describing resistance transition is proposed. Conduction mechanisms in the low resistive state are also discussed. Finally, the impact of oxide structure is studied.

Les nouvelles approches de technologies mémoires permettront une intégration dite back-end, où les cellules élémentaires de stockage seront fabriquées lors des dernières étapes de réalisation à grande échelle du circuit. Ces approches innovantes sont souvent basées sur l'utilisation de matériaux actifs présentant deux états de résistance distincts. Le passage d'un état à l'autre est contrôlé en courant ou en tension donnant lieu à une caractéristique I-V hystérétique. Nos mémoires résistives sont composées d'argent en métal électrochimiquement actif et de sulfure amorphe agissant comme électrolyte. Leur fonctionnement repose sur la formation réversible et la dissolution d'un filament conducteur. Le potentiel d'application de ces nouveaux dispositifs n'est pas limité aux mémoires ultra-haute densité mais aussi aux circuits embarqués. En empilant ces mémoires dans la troisième dimension au niveau des interconnections des circuits logiques CMOS, de nouvelles architectures hybrides et innovantes deviennent possibles. Il serait alors envisageable d'exploiter un fonctionnement à basse énergie, à haute vitesse d'écriture/lecture et de haute performance telles que l'endurance et la rétention. Dans cette thèse, en se concentrant sur les aspects de la technologie de mémoire en vue de développer de nouvelles architectures, l'introduction d'une fonctionnalité non-volatile au niveau logique est démontrée par trois circuits hybrides: commutateurs de routage non volatiles dans un Field Programmable Gate Arrays, un 6T-SRAM non volatile, et les neurones stochastiques pour un réseau neuronal. Pour améliorer les solutions existantes, les limitations de la performances des dispositifs mémoires sont identifiés et résolus avec des nouveaux empilements ou en fournissant des défauts de circuits tolérants. / Novel approaches in the field of memory technology should enable backend integration, where individual storage nodes will be fabricated during the last fabrication steps of the VLSI circuit. In this case, memory operation is often based upon the use of active materials with resistive switching properties. A topology of resistive memory consists of silver as electrochemically active metal and amorphous sulfide acting as electrolyte and relies on the reversible formation and dissolution of a conductive filament. The application potential of these new memories is not limited to stand-alone (ultra-high density), but is also suitable for embedded applications. By stacking these memories in the third dimension at the interconnection level of CMOS logic, new ultra-scalable hybrid architectures becomes possible which exploit low energy operation, fast write/read access and high performance with respect to endurance and retention. In this thesis, focusing on memory technology aspects in view of developing new architectures, the introduction of non-volatile functionality at the logic level is demonstrated through three hybrid (CMOS logic ReRAM devices) circuits: nonvolatile routing switches in a Field Programmable Gate Array, nonvolatile 6T-SRAMs, and stochastic neurons of an hardware neural network. To be competitive or even improve existing solutions, limitations on the memory devices performances are identified and solved by stack engineering of CBRAM devices or providing faults tolerant circuits.

abstract: Programmable Metallization Cell (PMC) technology has been shown to possess the necessary qualities for it to be considered as a leading contender for the next generation memory. These qualities include high speed and endurance, extreme scalability, ease of fabrication, ultra low power operation, and perhaps most importantly ease of integration with the CMOS back end of line (BEOL) process flow. One area where detailed study is lacking is the reliability of PMC devices. In previous reliability work, the low and high resistance states were monitored for periods of hours to days without any applied voltage and the results were extrapolated to several years (>10) but little has been done to analyze the low resistance state under stress. With or without stress, the low resistance state appears to be highly stable but a gradual increase in resistance with time, less than one order of magnitude after ten years when extrapolated, has been observed. It is important to understand the physics behind this resistance rise mechanism to comprehend the reliability issues associated with the low resistance state. This is also related to the erase process in PMC cells where the transition from the ON to OFF state occurs under a negative voltage. Hence it is important to investigate this erase process in PMC cells under different conditions and to model it. Analyzing the programming and the erase operations separately is important for any memory technology but its ability to cycle efficiently (reliably) at low voltages and for more than 1E4 cycles (without affecting the cells performance) is more critical. Future memory technologies must operate with the low power supply voltages (<1V) required for small geometry nodes. Low voltage programming of PMC memory devices has previously been demonstrated using slow voltage sweeps and small numbers of fast pulses. In this work PMC memory cells were cycled at low voltages using symmetric pulses with different load resistances and the distribution of the ON and OFF resistances was analyzed. The effect of the program current used during the program-erase cycling on the resulting resistance distributions is also investigated. Finally the variation found in the behavior of similar resistance ON states in PMC cells was analyzed more in detail and measures to reduce this variation were looked into. It was found that slow low current programming helped reducing the variation in erase times of similar resistance ON states in PMC cells. This scheme was also used as a pre-conditioning technique and the improvements in subsequent cycling behavior were compared. / Dissertation/Thesis / Ph.D. Electrical Engineering 2011

abstract: Advances in software and applications continue to demand advances in memory. The ideal memory would be non-volatile and have maximal capacity, speed, retention time, endurance, and radiation hardness while also having minimal physical size, energy usage, and cost. The programmable metallization cell (PMC) is an emerging memory technology that is likely to surpass flash memory in all the listed ideal memory characteristics. A comprehensive physics-based model is needed to fully understand PMC operation and aid in design optimization. With the intent of advancing the PMC modeling effort, this thesis presents two simulation models for the PMC. The first model is a finite element model based on Silvaco Atlas finite element analysis software. Limitations of the software are identified that make this model inconsistent with the operating mechanism of the PMC. The second model is a physics-based numerical model developed for the PMC. This model is successful in matching data measured from a chalcogenide glass PMC designed and manufactured at ASU. Matched operating characteristics observable in the current and resistance vs. voltage data include the OFF/ON resistances and write/erase and electrodeposition voltage thresholds. Multilevel programming is also explained and demonstrated with the numerical model. The numerical model has already proven useful by revealing some information presented about the operation and characteristics of the PMC. / Dissertation/Thesis / PMC numerical model written in M for Octave/MATLAB / M.S. Electrical Engineering 2013

No description available.

Integrating nanometer-sized pores into low-k ILD films is one of the approaches to lower the RC signal delay and thus help sustain the continued scaling of microelectronic devices. While increasing porosity of porous dielectrics lowers the dielectric constant (k), it also creates many reliability and implementation issues. One of the problems is the little understood metal ion diffusion and drift in porous media. Here, we present a rigorous simulation method of Cu diffusion based on Master equation with elementary jump probabilities within the contiguous dielectric film, along the pore boundary, from the dielectric matrix to the pore boundary, and from the pore boundary to the matrix material. In view of the diffusional jump distance being as large as 2 nm, the nano-pores being on a similar length scale, and the film thickness being only a few tens of nanometers, the conventional diffusion equation in differential equation form is grossly inadequate and elementary jump frequencies are required for a proper description of the Cu diffusion in porous dielectric. The present atomistic approach allows a consistent implementation of Cu ion drift in electric field by lowering and raising of the diffusion barriers along the field direction. This will help understand the behavior of Cu interconnects under thermal or electric stress at an atomistic level. Another approach to lower the increasing RC delays is to bring memory and logic closer by integrating memory in the BEOL. Resistive RAM is one such memory is not transistor based and thus, does not require a silicon substrate. Thus, it offers the possibility of integration directly into the back-end reducing memory to logic distance from 1000s of µm to a 10s of nm. This 3D integration also allows for increased density as well. However, one barrier in the implementation of RRAM in the back end is the use of expensive as well as non-BEOL native material in conventional Cu/TaOx/Pt resistive devices. In this thesis, we present our research about functionality of RRAM with porous low-k dielectrics (which are a candidate for CMOS ILD), and through the similar elementary jump simulations, discuss the impact of porosity in dielectrics on the functionality of RRAM. Lastly, we present a cheaper replacement for Pt as the counter electrode in RRAM and show that it functions as good as Pt. This work addresses following three areas: 1. Modeling of diffusion in porous dielectrics through elementary jump based simulation. The model is based on random walk theory of elementary particle jumps. Initially, qualitative simulations are conducted without actual parameters. It is shown that Cu diffusion in porous dielectrics decreases quasi-linearly with porosity. Furthermore, it is shown that morphology of the pores may have a greater effect on diffusivity compared to porosity. The simulations are then calibrated with parameters, and the result is shown to yield a similar diffusivity times as actual process time. 2. Modeling of Cu ions drift in porous dielectrics under electric stress. First, the model is explained, and then qualitative simulation results are presented for porous dielectrics with varied porosities and morphologies. 3. Research to find a suitable replacement for Pt as the counter electrode in RRAM devices. The research methodology is discussed and a much cheaper Rh is selected as the potential replacement for Pt. Successful functionality of Rh based resistive devices is presented. / Master of Science / As electronic devices are being scaled for integrating more functions and higher computation, the internal delays are increasing, which may become a bottleneck in performance. To resolve this issue of internal delay, new materials are being proposed to replace the conventional materials to make the chip. One promising material like that are the porous dielectrics, to replace the conventional dielectrics used to manufacture electronic chips. The introduction of ‘air pores’ inside the dielectric used in chips may improve the delay, but it leads to several thermal and electrical reliability concerns. In this thesis, we argue that using differential equations to simulate effects on the nano-scale to explore such reliability issues is insufficient, and a simulation method based on individual atom/ion movement should be used to describe it. Here we provide a simulation model to explain the diffusivity of copper under thermal stress, as well as movement of Cu ions during electric stress in porous dielectrics, using our particle movement based simulation model, and prove that it delivers correct results. Secondly, the delay is especially significant for processor to memory communication. Thus, integrating memory close to processor is another method to reduce the delay. Resistive RAM (RRAM) is one such novel RAM technology that can be integrated close to processor. However due to usage of non-native as well as expensive materials, RRAM has not been commercially integrated close to processor. In this thesis, we also present a functioning RRAM using cheaper materials, as well as materials that are native to present electronics.

Les mémoires non-volatiles sont devenues récemment un moteur clé de la croissance du secteur des semiconducteurs, et constituent un pivot pour les nouvelles applications et les nouveaux concepts dans le domaine des technologies de l'information et de la communication (TIC). Afin de surmonter les limites en termes de miniaturisation, de consommation électrique et de complexité de fabrication des mémoires non-volatiles à grille flottante (FLASH), l'industrie des semiconducteurs évalue actuellement des solutions alternatives. Parmi celles-ci, les mémoires résistives à pont conducteur ou CBRAM (Conductive Bridge Random Access Memory), qui reposent sur la commutation de résistance d'un électrolyte par migration et oxydo/réduction d'ions métalliques, semblent être des plus prometteuses. L'attractivité de cette technologie innovante vient d'une part de la simplicité de sa structure à deux terminaux et d'autre part de ses performances électriques très prometteuses en termes de consommation électrique et vitesse d'écriture/effacement. De surcroît la CBRAM is une technology mémoire qui s'intègre facilement dans le back end of line (BEOL) du procédé CMOS standard. Dans cette thèse, nous étudions les performances électriques et la fiabilité de deux technologies CBRAM, utilisant des chalcogénures (GeS2) ou un oxyde métallique pour l'électrolyte. Tout d'abord nous nous concentrons sur les CBRAM à base de GeS2, ou l'effet du dopage de l'électrolyte avec de l'argent (Ag) ou de l'antimoine (Sb) est étudié à la lumière d'une analyse des caractérisations électriques. Les mécanismes physiques gouvernant la cinétique de commutation et la stabilité thermique sont aussi discutés sur la base de mesures électrique, d'un modèle empirique et des résultats de calculs ab initio. L'influence des différentes conditions de set/reset est étudiée sur une CBRAM à base d'oxyde métallique. Grâce à cette analyse, les conditions permettant de maximiser la fenêtre mémoire, améliorer l'endurance et minimiser la variabilité sont déterminées. / Non-volatile memory technology has recently become the key driver for growth in the semiconductor business, and an enabler for new applications and concepts in the field of information and communication technologies (ICT). In order to overcome the limitations in terms of scalability, power consumption and fabrication complexity of Flash memory, semiconductor industry is currently assessing alternative solutions. Among them, Conductive Bridge Memories (CBRAM) rely on the resistance switching of a solid electrolyte induced by the migration and redox reactions of metallic ions. This technology is appealing due to its simple two-terminal structure, and its promising performances in terms of low power consumption, program/erase speed. Furthermore, the CBRAM is a memory technology that can be easily integrated with standard CMOS technology in the back end of line (BEOL). In this work we study the electrical performances and reliability of two different CBRAM technologies, specifically using chalcogenides (GeS2) and metal oxide as electrolyte. We first focus on GeS2-based CBRAM, where the effect of doping with Ag and Sb of GeS2 electrolyte is extensively investigated through electrical characterization analysis. The physical mechanisms governing the switching kinetics and the thermal stability are also addressed by means of electrical measurements, empirical model and 1st principle calculations. The influence of the different set/reset programming conditions is studied on a metal oxide based CBRAM technology. Based on this analysis, the programming conditions able to maximize the memory window, improve the endurance and minimize the variability are determined.