As power conversion technology is being integrated further into high-reliability environments such as aerospace and electric vehicle applications, a full analysis and understanding of the system's robustness under operating conditions inside and outside the safe-operating-area is necessary. The robustness of power semiconductor devices, a primary component of power converters, has been traditionally evaluated through qualification tests that were developed for legacy silicon (Si) technologies. However, new devices have been commercialized using wide bandgap (WBG) semiconductors including silicon carbide (SiC) and gallium nitride (GaN). These new devices promise enhanced capabilities (e.g., higher switching speed, smaller die size, lower junction capacitances, and higher thermal conductance) over legacy Si devices, thus making the traditional qualification experiments ineffective. This work begins by introducing a new methodology for evaluating the switching robustness of SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). Recent static acceleration tests have revealed that SiC MOSFETs can safely operate for thousands of hours at a blocking voltage higher than the rated voltage and near the avalanche boundary. This work evaluates the robustness of SiC MOSFETs under continuous, hard-switched, turn-off stresses with a dc-bias higher than the device rated voltage. Under these conditions, SiC MOSFETs show degradation in merely tens of hours at 25si{textdegree}C and tens of minutes at 100si{textdegree}C. Two independent degradation and failure mechanisms are unveiled, one present in the gate-oxide and the other in the bulk-semiconductor regions, detected by the increase in gate leakage current and drain leakage current, respectively. The second degradation mechanism has not been previously reported in the literature; it is found to be related to the electron hopping along the defects in semiconductors generated in the switching tests. The comparison with the static acceleration tests reveals that both degradation mechanisms correlate to the high-bias switching transients rather than the high-bias blocking states. The GaN high-electron-mobility transistor (HEMT) is a newer WBG device that is being increasingly adopted at an unprecedented rate. Different from SiC MOSFETs, GaN HEMTs have no avalanche capability and withstand the surge energy through capacitive charging, which often causes significant voltage overshoot up to their catastrophic limit. As a result, the dynamic breakdown voltage (BV) and transient overvoltage margin of GaN devices must be studied to fully evaluate the switching ruggedness of devices. This work characterizes the transient overvoltage capability and failure mechanisms of GaN HEMTs under hard-switched turn-off conditions at increasing temperatures, by using a clamped inductive switching circuit with a variable parasitic inductance. This test method allows flexible control over both the magnitude and the dV/dt of the transient overvoltage. The overvoltage robustness of two commercial enhancement-mode (E-mode) p-gate HEMTs was extensively studied: a hybrid drain gate injection transistor (HD-GIT) with an Ohmic-type gate and a Schottky p-Gate HEMT (SP-HEMT). The overvoltage failure of the two devices was found to be determined by the overvoltage magnitude rather than the dV/dt. The HD-GIT and the SP-HEMT were found to fail at a voltage overshoot magnitude that is higher than the breakdown voltage in the static current-voltage measurement. These single event failure tests were repeated at increasing temperatures (100si{textdegree}C and 150si{textdegree}C), and the failures of both devices were consistent with room temperature results. The two types of devices show different failure behaviors, and the underlying mechanisms (electron trapping) have been revealed by physics-based device simulations. Once this single-event overvoltage failure was established, the device's robustness under repetitive overvoltage and surge-energy events remained unclear; therefore, the switching robustness was evaluated for both the HD-GIT and SP-HEMT in a clamped, inductive switching circuit with a 400 V dc bias. A parasitic inductance was used to generate the overvoltage stress events with different overvoltage magnitude up to 95% of the device's destructive limit, different switching periods from 10 ms to 0.33 ms, different temperatures up to 150si{textdegree}C, and different negative gate biases. The electrical parameters of these devices were measured before and after 1 million stress cycles under varying conditions. The HD-GITs showed no failure or permanent degradation after 1-million overvoltage events at different switching periods, or elevated temperatures. The SP-HEMTs showed more pronounced parametric shifts after the 1 million cycles in the threshold voltage, on-resistance, and saturation drain current. Different shifts were also observed from stresses under different overvoltage magnitudes and are attributable to the trapping of the holes produced in impact ionization. All shifts were found to be recoverable after a relaxation period. Overall, the results from these switching-oriented robustness tests have shown that SiC MOSFETs show a tremendous lifetime under static dc-bias experiments, but when excited by hard-switching turn-off events, the failure mechanisms are accelerated. These results suggest the insufficient robustness of SiC MOSFETs under high bias, hard switching conditions, and the significance of using switching-based tests to evaluate the device robustness. These inspired the GaN-based hard-switching turn-off robustness experiments, which further demonstrated the dynamic breakdown voltage phenomena. Ultimately these results suggest that the breakdown voltage and overvoltage margin of GaN HEMTs in practical power switching can be significantly underestimated using the static breakdown voltage. Both sets of experiments provide further evidence for the need for switching-oriented robustness experiments to be implemented by both device vendors and users, to fully qualify and evaluate new power semiconductor transistors. / Doctor of Philosophy / Power conversion technology is being integrated into industrial and commercial applications with the increased use of laptops, server centers, electric vehicles, and solar and wind energy generation. Each of these converters requires the power semiconductor devices to convert energy reliably and safely. textcolor{black}{Silicon has been the primary material for these devices; however,} new devices have been commercialized from both silicon carbide (SiC) and gallium nitride (GaN) materials. Although these devices are required to undergo qualification testing, the standards were developed for silicon technology. The performance of these new devices offers many additional benefits such as physically smaller dimensions, greater power conversion efficiency, and higher thermal operating capabilities. To facilitate the increased integration of these devices into industrial applications, greater robustness and reliability analyses are required to supplement the traditional tests. The work presented here provides two new experimental methodologies to test the robustness of both SiC and GaN power transistors. These methodologies are oriented around hard-switching environments where both high voltage biases and high conduction current exist and stress the intrinsic semiconductor properties. Experimental evaluations were conducted of both material technologies where the electrical properties were monitored over time to identify any degradation effects. Additional analyses were conducted to determine the physics-oriented failure mechanisms. This work provides insight into the limitations of these semiconductor devices for both device designers and manufacturers as well as power electronic system designers.

As wide-bandgap devices continue to experience deeper penetration in commercial applications, there are still a number of factors which make the adoption of such technologies difficult. One of the most notable issues with the application of wide-bandgap technologies is meeting existing noise requirements and regulations. Due to the faster dv/dt and di/dt of SiC devices, more noise is generated in comparison to Si IGBTs. Therefore, in order to fully experience the benefits offered by this new technology, the noise must either be filtered or mitigated by other means. A survey of various DC/DC topologies was conducted in order to find a candidate for a battery interface in a UPS system. A three-level NPC topology was explored for its potential benefit in terms of noise, efficiency, and additional features. This converter topology was modeled, simulated, and a hardware prototype constructed for evaluation within a UPS system, although its uses are not limited to such applications. A UPS system is a good example of an application with strict noise requirements which must be fulfilled according to IEC standards. Based on a newly devised mode of operation, this converter was verified to produce no common-mode voltage under ideal conditions, and was able to provide a 6 dB reduction in common-mode voltage emissions in the UPS prototype. This was done while achieving a peak efficiency in excess of 99% with the ability to provide bidirectional power flow between the UPS and battery backup. The converter was verified to operate at the rated UPS conditions of 20 kW while converting between a total DC bus voltage of 800 V and a nominal battery voltage of 540 V. / Master of Science / As material advancements allow for the creation of devices with superior electrical characteristics compared to their predecessors, there are still a number of factors which cause these devices to see limited usage in commercial applications. These devices, typically referred to as wide-bandgap devices, include silicon carbide (SiC) transistors. These SiC devices allow for much faster switching speeds, greater efficiencies, and lower system volume compared to their silicon counterparts. However, due to the faster switching of these devices, there is more electromagnetic noise generated. In many applications, this noise must be filtered or otherwise mitigated in order to meet international standards for commercial use. Consequently, new converter topologies and configurations are necessary to provide the most benefit of the new wide-bandgap devices while still meeting the strict noise requirements. A survey of topologies was conducted and the modeling, design, and testing of one topology was performed for use in an uninterruptible power supply (UPS). This converter was able to provide a noticeable reduction in noise compared to standard topologies while still achieving very high efficiency at rated conditions. This converter was also verified to provide power bidirectionally—both when the UPS is charging the battery backup, and when the battery is supplying power to the load.

Neutral-point-clamped (NPC) three-level inverter is capable of handling higher dc bus voltage and producing output waveform of better quality than a conventional two-level inverter. The main objective of the present work is to analyze the existing PWM schemes for two-level and three-level inverters in terms of line current ripple, and to design new PWM techniques for the NPC inverter to reduce line current distortion. Various discontinuous PWM or bus-clamping PWM (BCPWM) methods for a two-level voltage source inverter are analyzed in terms of rms line current ripple, which is evaluated by integrating the error voltage (i.e. error between the applied and reference voltages). The BCPWM schemes can be broadly classified into continual-clamp PWM (CCPWM) and split-clamp PWM (SCPWM). It is shown that split-clamp PWM scheme leads to lower harmonic distortion than CCPWM scheme. Further, advanced bus-clamping PWM (ABCPWM) methods for a two-level inverter are also studied. These methods clamp each phase to the positive and negative DC terminals over certain intervals as in BCPWM schemes, and also switch each phase at double the nominal frequency in certain other intervals unlike in BCPWM. Analytical closed-form expressions are derived for the total rms harmonic distortion due to SCPWM, CCPWM and ABCPWM schemes. Existing sinusoidal and bus-clamping PWM schemes for three-level NPC inverters are also analyzed in the space vector domain. These methods are compared in terms of line current ripple analytically as well as experimentally. As earlier, closed-form expressions are derived for the harmonic distortion factors corresponding to centered space vector PWM (CSVPWM) and the various BCPWM methods. A three-level inverter can be viewed as an equivalent two-level inverter in each sixth of the fundamental cycle or hextant. This is widely used to simplify the control of an NPC inverter. Further, this approach makes it simple to extend the BCPWM and ABCPWM methods for two-level inverters to three-level inverters. Furthermore, the method of analysis of line current ripple for the two-level inverter can also be easily extended to the three-level case. The pivot vector, which is half the length of the longest voltage vectors produced by the NPC inverter, acts as an equivalent null vector for the conceptual two-level inverter. Each pivot vector can be produced by two inverter states termed as “pivot states”. Typically, in continuous modulation methods for NPC inverter such as sinusoidal PWM and centered space vector PWM, the switching sequence (i.e. the sequence in which the voltage vectors are applied) begins and ends with the same pivot vector in each subcycle, which is equivalent to a half-carrier cycle. To be more precise, the switching sequence starts with one pivot state and ends with the other in each subcycle. However, in case of BCPWM schemes, only one pivot state is used in a subcycle. The choice of pivot state results in a variety of BCPWM schemes for an NPC inverter. Different BCPWM schemes are evaluated in terms of rms line current ripple. The optimal BCPWM, which minimizes the rms current ripple, is determined for an NPC inverter, controlled as an equivalent two-level inverter. Further, four new switching sequences are proposed here for a three-level inverter, controlled as a conceptual two-level inverter. These sequences apply the pivot vector only once, but employ one of the other two vectors twice within the subcycle. These four switching sequences are termed as “ABCPWM sequences” for three-level inverter. These sequences exploit the flexibility available in the space vector approach to PWM to switch a phase more than once in a subcycle, which results in the application of an active vector twice within the subcycle. Influence of the proposed ABCPWM sequences on the line current ripple over a subcycle is studied. The various sequences are compared in terms of rms line current ripple over a subcycle. An analytical closed-form expression for rms line current ripple over a subcycle is derived in terms of reference magnitude, angle of reference voltage vector, and subcycle duration for each of the sequences. Further, closed-form expressions are also derived for the rms current ripple over a line cycle in terms of modulation index and subcycle duration, corresponding to the various sequences. The four proposed ABCPWM sequences for the NPC inverter can be grouped into two pairs of sequences. Each pair of sequences is shown to perform better than the individual sequences, if the two sequences are employed in appropriate spatial regions. Hence, with these two pairs of sequences, two hybrid PWM schemes are proposed. Finally, a hybrid PWM technique is proposed which employs all five sequences (conventional and proposed four sequences) in spatial regions where each performs the best. This is termed as “five-zone hybrid PWM”. The total harmonic distortion (THD) in the motor current, pertaining to all the proposed schemes, is studied theoretically over the entire range of linear modulation. The theoretical investigations are validated experimentally on a 2.2 kW, 415V, 4.9A, 50 Hz induction motor drive. The no-load current THD is measured over a range of fundamental frequency from 10 Hz to 50 Hz in steps of 2 Hz for the various PWM methods. Theoretical and experimental results bring out the reduction in current THD due to the proposed BCPWM schemes at fundamental frequencies of 45 Hz and above, compared to CSVPWM. The ABCPWM methods improve the performance at higher as well as lower modulation indices. Further improvement is achieved with the proposed five-zone hybrid PWM. At the rated frequency (50 Hz) of the drive, the improvement in line current distortion is around 36% with this hybrid PWM scheme over CSVPWM. The reduction in THD is also experimentally verified at different loads on the motor. The difference between the top and bottom capacitor voltages is measured at various operating conditions, corresponding to CSVPWM and the proposed schemes. No significant difference is observed in the dc neutral voltage shifts with the different proposed schemes and CSVPWM method. Thus, the proposed methods improve the THD at low and high speed ranges without appreciable worsening of the dc voltage unbalance.

This thesis project focuses on the simulation, design, hardware realization, and performance evaluation of a Three-phase Three-level (3-L) Sparse Neutral Point Clamped Converter (SNPCC) for Industrial Variable Speed Drives (VSDs). The basic operating principle of the SNPCC is briefly described based on switching functions. Accordingly, the modulation strategies as a combination of switching sequences are introduced. Three representative strategies are selected to be verified in this project. Afterward, active and passive components are selected based on analytical analysis mainly focusing on semiconductors losses, AC-side differential mode and common mode stresses. Meantime, the analytical analysis enables a straightforward performance comparison among the selected modulation strategies. Additionally, the reverse recovery process in the anti-parallel diode is identified, of which the energy losses are calculated. A calorimetric method is adopted in this project, which allows accurate temperature rise monitoring and provides a reliable way to measure the power losses generated by semiconductors. Eventually, an 800V 7.5kW prototype is constructed and put under test. The performance of the designed SNPCC is therefore evaluated and compared from losses and AC-side flux-linkage ripples perspectives, with the promising features highlighted and limits indicated. / Projektet fokuserar på simulering, konstruktion, hårdvarutillverkning och utvärdering av en trefas tre-nivå (3-L) Sparse Neutral Point Clamped Converter (SNPCC) för industriella varvtalsstyrda motordrifter (VSD). SNPCC:s grundläggandefunktionsprincip beskrivs kortfattat utifrån så kallade switchningsfunktioner. Därefter introduceras moduleringsstrategierna som en kombination av switchningssekvenser. Tre representativa strategier har valts ut för att verifieras i detta projekt. Därefter väljs aktiva och passiva komponenter på grundval av en analys som främst fokuserar på halvledarförluster och ledningsbundna störningar på växelsströmssidan. Analysen gör det möjligt att göra en enkel jämförelse av prestanda mellan de valda moduleringsstrategierna. Dessutom identifieras body-diodens återhämtningsprocess och energiförlusterna beräknas. I detta projekt används en kalorimetrisk förlustberäkning, som möjliggör noggrann övervakning av temperaturökningen och ger ett tillförlitligt sätt att mäta energiförlusterna i effekthalvledarna. Slutligen konstrueras och testas en 800V 7.5kW-prototyp. Prestandan hos den konstruerade SNPCC:n utvärderas med hänseende till förluster och flödesrippel på växelströmssidan. Fördelarna för den föreslagna tekniken lyfts fram och begränsningarna anges.

CoordenaÃÃo de AperfeiÃoamento de Pessoal de NÃvel Superior / Visando superar os desafios inerentes à conversÃo de energia elÃtrica em sistemas de alta potÃncia, minimizando as perdas e melhorando a qualidade da energia processada, este tra-balho tem por objetivo analisar e implementar uma tÃcnica de modulaÃÃo para ser aplicada nas duas topologias de inversores multinÃveis mais disseminadas - com neutro grampeado (NPC), e com capacitor flutuante (FC) - a fim de reduzir os esforÃos nos semicondutores, bem como melhorar o Ãndice de distorÃÃo harmÃnica da tensÃo de saÃda. Ao longo do trabalho foi evidenciada a necessidade da digitalizaÃÃo da tÃcnica proposta, visto que o desenvolvimento analÃgico da mesma acarretaria em um circuito complexo e de baixa confiabilidade. Dessa forma, escolheu-se como plataforma digital um FPGA, devido à sua facilidade de programa-ÃÃo e reconfiguraÃÃo, alÃm da alta velocidade e quantidade de pinos de entrada e saÃda. AlÃm da tÃcnica proposta, foram tambÃm desenvolvidas outras modulaÃÃes para fins de compara-ÃÃo, apresentando os padrÃes de chaveamento para cada uma delas, bem como o comporta-mento da corrente atravÃs dos semicondutores em cada perÃodo de chaveamento. Foi tambÃm realizada a anÃlise teÃrica das topologias e suas respectivas etapas de operaÃÃo, caracterÃsticas e levantamento das equaÃÃes que ditam a anÃlise das perdas para as diferentes situaÃÃes de tÃcnicas aplicadas a cada uma das estruturas. O desenvolvimento digital das tÃcnicas mostrou-se correta atravÃs da anÃlise das formas-de-onda colhidas por meio de um circuito digital-analÃgico. AlÃm disso, a comparaÃÃo da aplicaÃÃo dessas modulaÃÃes em inversores a trÃs nÃveis NPC e FC de 6 kW mostrou-se favorÃvel à tÃcnica proposta em termos de eficiÃncia e reduÃÃo da distorÃÃo harmÃnica em ambas as topologias, comprovando sua utilidade em con-versores multinÃveis de alta potÃncia. Por fim, foi apresentado o desenvolvimento da tÃcnica proposta em inversores com mais de trÃs nÃveis, onde se pode comprovar sua eficiente aplica-ÃÃo para tais fins, bem como sua expansibilidade para inversores de n nÃveis. / In order to overcome the challenge of processing electric energy in high power systems with minimal losses and high energy quality, this work presents the implementation and anal-ysis of a modulation technique applicable on both most well-known multilevel inverter struc-tures - neutral point-clamped (NPC), and flying capacitors (FC) - to reduce the stresses across the semiconductors devices, and to improve the total harmonic distortion of the output volt-age. Throughout the work, the necessity to digitalize the proposed technique has been evi-denced due to the high complexity and low reliability inherent to the analogical approach. Thus, the digital controller FPGA has been chosen, as it is easy to program and reconfigure, works at high speed, and has a lot of input and output pins. Additionally, other modulation techniques were also implemented to compare their performance with the proposed one, pre-senting the switching patterns and the behavior of the electrical currents through the semicon-ductors for each modulation. A theoretical analysis was also performed for both topologies and their respective operation principle, characteristics, and equations used on the losses anal-ysis for the different combinations of modulation applied to each structure. Finally, the digital development of the various techniques has proved to be correct by observing the waveforms obtained through the digital/analogical circuit. Besides, the comparison of the modulation techniques on 6 kW NPC and FC three-level prototype inverters proved to be favorable to the proposed technique in terms of efficiency and total harmonic distortion reduction on both topologies, confirming its usefulness on high power multilevel converters. At last, it was pre-sented the application of the proposed modulation technique to inverters with more than three levels, where it was observed its eligibility for n-levels topologies.

Seventy-four methicillin-resistant Staphylococcus aureus (MRSA) from two Malaysian hospitals were characterised by both phenotypic and genotypic techniques. These isolates were collected over an 18 year time period in the years, 1982, 1989, 1994 and 2000. All of the Malaysian MRSA isolates were found to be multiresistant and resistant to at least five different antimicrobial agents. Over 30% of them were non-typable by the International Basic Set of bacteriophages. The majority of the typable isolates were susceptible to the group III phages, especially phage 85. The majority of the isolates carried one to six plasmids. Only two isolates were plasmid free. The plasmid profiles of these isolates, other than the 1982 isolates, were very similar to each other. Contour-clamped homogeneous electric field (CHEF) gel electrophoresis was used to examine the genetic relatedness of the isolates. Twenty-six CHEF patterns were found among the isolates. These CHEF patterns were closely related to each other. The predominant CHEF pattern A was found in the 1982, 1989 and 1994 isolates. The CHEF patterns of the year 2000 isolates were different to CHEF pattern A, but still closely related. All of the isolates were found to carry the Allotype III SCCmec and have coagulase-gene type 24. Multilocus sequence typing was preformed on the isolates with CHEF pattern A collected in different years. These isolates were found to have either sequence type 239 (ST239), or its single locus variant. The predominant Malaysian clone belongs to the pandemic clone ST239-MRSA-III that is pandemic in Asian countries. (Enright, 2003, Ko et al., 2005). / A 1.5 kb cryptic plasmid found in Malaysian isolates was indistinguishable from a cryptic plasmid found in an Australian isolate. A 3.0 kb cryptic plasmid found in Malaysian isolates was undistinguishable from a 3.0 kb plasmid found in Singaporean isolates. Class II multiresistance plasmids of 28, 30.5 and 35 kb were commonly found together in many Malaysian MRSA isolates. Both the 28 and 30.5 kb plasmids encode resistance to the heavy-metals and nucleic acid-binding (NAB) compounds. The 35 kb plasmid carries heavy-metal and NAB resistance but also encodes β-lactamase. Structurally these three plasmids are almost identical and probably have the same origin. The differences observed between these plasmids is probably due to excision or partial deletion of the β-lactamase transposon of the original plasmid. The 28 kb plasmid is identical to the 28 kb plasmid of Singaporean and some Australian isolates. A 20 kb plasmid in Indonesian isolates was found to be closely related to these three plasmids. A conjugative plasmid, pWBG707, conferring trimethoprim-resistance was found in Malaysian isolates. It did not carry either of the two staphylococcal trimethoprim-resistance genes, dfrA and dfrD. (Lyon and Skurray, 1987, Dale et al., 1995b) It either encodes a novel resistance gene or the recently discovered dfrG gene. (Sekiguchi et al., 2005) pWBG707 was also found to mobilise a small 3.0 kb kanamycin-resistance plasmid during conjugation. / The mecR1 and mecI genes regulating the transcription of the methicillin-resistance gene, mecA, were also examined in the isolates. The Malaysian isolate, WBG7422, with the predominant CHEF pattern A has a nonsense mutation in its mecI gene that disables it. However, its mecR1 gene is intact. The eastern Australia MRSA (EA MRSA), WBG525, has a CHEF pattern that is closely related to the Malaysian predominant CHEF pattern A and its mecI gene has a mutation identical to the Malaysian isolate. Unlike the Malaysian isolate however, its mecR1 gene has a 166 bp deletion. Both WBG7422 and WBG525 express Class III heterogeneous methicillin resistance. However, WBG525 has more highly resistant cell in its population than WBG7422. The loss of aminoglycoside resistance, together with c. 114 kb of chromosomal DNA, was observed in some Malaysian isolates. The deleted segment was found to carry the aacA-aphD gene that encodes a bifunctional aminoglycoside-modifying enzyme conferring resistance to many of the aminoglycosides. The Malaysian isolates were compared with MRSA from different countries. These MRSA included 18 epidemic MRSA (EMRSA) from the United Kingdom, 15 Australian nosocomial MRSA, five classical MRSA, 22 community-acquired MRSA (CMRSA) from Australia and New Zealand and 46 nosocomial MRSAs from eight Asian-Pacific countries and South Africa. These Asian-Pacific countries were Australia, PR China, Hong Kong, Indonesia, Japan, Philippines, Singapore and Taiwan. / The CHEF patterns of most of the Asian-Pacific and South African isolates were closely related to the Malaysian isolates. Isolates from Singapore, Indonesia and Philippines were found to have an identical CHEF pattern to the Malaysian CHEF patterns A5. The Asian-Pacific and South African isolates, including the Malaysian isolates, were found to be closely related to EMRSA-1, -4 and -7. These EMRSA belong to the ST239-MRSA-III clone and are coagulase-gene type 24. The isolates from Japan were the only Asian-Pacific isolates not related to the other Asian-Pacific isolates and EMRSAs. EMRSA-1 and EA MRSA have the same 166 bp deletion in their mecR1 gene. Both of these strains have closely related CHEF patterns, the same sequence type, coagulase-gene type and SCCmec. These results indicate that these two strains belongs to the same clone and confirms the international spread of this clone in the early 1980s. However, the Malaysian isolates have CHEF patterns that are more closely related to EMRSA-4 than to EMRSA-1. Similar to the Malaysian isolates EMRSA-4 has an intact mecR1 gene. The CMRSA isolates were not related to any of the nosocomial MRSA. They also have very diverse genetic backgrounds but carry less diverse SCCmec allotypes. Most of the CMRSA carry either Allotype IV or V SCCmec These results show that the spread of Malaysian MRSA is due to a single clonal expansion. Infection control measures would have to have been more efficient if this clone was to have been contained. The Malaysian epidemic clone is the Asian pandemic clone, ST239-MRSA-III. The Malaysian isolates and EMRSA-4 probably share the same ancestor. / The presence of the same MRSA strain in Malaysian hospitals and in the hospitals of neighbouring countries indicates that the inter-hospital spread of an epidemic MRSA has occurred. This observation also suggests that the infection control measures in Malaysian hospitals have not been totally effective. The ineffectiveness of infection control has left Malaysian hospitals vulnerable to the future importation of new pandemic clones and/or highly virulent or resistant clones.

Made available in DSpace on 2016-12-12T20:27:38Z (GMT). No. of bitstreams: 1 Tiago Lemes.pdf: 2229669 bytes, checksum: 9b9cd44356c6d0002fccf67fe418f52b (MD5) Previous issue date: 2014-09-26 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / The main subject of this work is the study of a 5 levels T-Type NPC inverter topology, which is applied in photovoltaic energy processing for power generation. The grid power injection is done controlling converter current, which is injected into grid. This work presents equations, component-designs and their validation, which are necessary for the Inverter s power structure implementation. Also inverter modeling and design of implemented controllers are described. Through this study, it was possible to build a 3 kW prototype, which besides the current control, has a system to balance the differential voltage of bus capacitors. Through the prototype, experimental results were acquired. / O objeto de estudo deste trabalho é a topologia inversora NPC T-Type 5 níveis, aplicada no processamento da energia fotovoltaica, sendo o principal objetivo a geração de energia elétrica por meio do controle da corrente aplicada à rede. Este trabalho apresenta o equacionamento, projeto dos componentes e sua validação, que fazem parte da estrutura de potência do inversor, bem como a sua modelagem e projeto dos controladores implementados. Por intermédio deste estudo foi possível construir um protótipo com potência nominal de 3 kW, que além do controle da corrente, apresenta uma malha de equilíbrio da tensão diferencial do barramento. Mediante construção desse protótipo, foram extraídos os resultados experimentais.

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior / This dissertation deals with modulation techniques for multilevel diode clamped converters. The major challenge to be overcome by modulation strategies to these converters is the balance of the dc-link voltage capacitors, whilst minimizing the THD of output voltages. Among the modulation strategies reported in literature for this purpose are the carrier-based and space vector modulation techniques. Generally the space vetor methods select the nearest three vector to implement the desired output voltage vector. However, it is not always possible to remove the low frequency ripple in the dc-link voltage capacitors using this diagram vector. This work proposes a new space vector diagram that allows the elimination of the low frequency ripple in the dc-link voltage capacitors and guarantees the balance to the entire converter linear operation region, operating with any power factor load. Further constrains are derived based on the sign and magnitude of the output currents to determine the transition between the space vector diagram N3V and NS3V, making a hybrid modulation. As a result is possible to minimize the total harmonic distortion of the output voltages and to ensure the control of the averaged neutral point current. In order to make it possible to extend the results for converters with any number of levels, a carrier based modulation was proposed in this work where the modulation signals are chosen to ensure maximum use of the dc-link of the linear range of operation of converter, and eliminate low-frequency oscillation in the voltage capacitors. Moreover, it is proposed a space vector modulation strategy to back-to-back three level diode clamped converters, with the purpose to connect the wind power generation to the grid. This technique combines the utilization of the N3V and NS3V space vector diagrams for both converters connected to the same dc-link. Thus it is possible to establish a trade off between oscillation in the voltage capacitors and THD of output voltages. Experimental results and benchmarks are presented and demonstrate the good performance of the proposed methods. / Esta dissertação de mestrado trata de estratégias de modulação para conversores multiníveis com diodos de grampeamento. O principal desafio a ser superado por técnicas de modulação aplicadas a estes conversores é o de equilibrar as tensões dos capacitores do barramento CC, enquanto que minimizando a penalização da THD das tensões de saída. Dentre as principais estratégias de modulação com esse propósito abordadas na literatura, são as estratégias baseadas na comparação com portadora e as estratégias vetoriais. Geralmente os métodos de modulação vetorial utilizam os três vetores de comutação mais próximos do vetor de tensão de referência, N3V. Entretanto nem sempre é possível eliminar as ondulações de baixa frequência presentes nas tensões dos capacitores do barramento CC em toda faixa de operação do conversor utilizando essa divisão de setores. Este trabalho deriva um novo diagrama vetorial NS3V, que possibilita a eliminação das ondulações de baixa frequência das tensões dos capacitores do barramento CC na região linear do conversor, independente do fator de potência de operação. Além disso são obtidas restrições baseadas no sinal e nas magnitudes das correntes de saída para determinar a transição entre a modulação que utiliza o diagrama vetorial N3V e o diagrama vetorial NS3V, tornando a modulação híbrida. Com isto é possível minimizar a distorção harmônica das tensões de saída e assegurar o controle da corrente média sobre um período de comutação no ponto central do divisor capacitivo. Com objetivo de facilitar a extensão dos resultados para um número qualquer de níveis, a modulação baseada na comparação com portadora foi proposta nesse trabalho onde as tensões modulantes são escolhidas de forma a garantir a máxima utilização da tensão do barramento CC na faixa linear de operação do conversor, bem como eliminar as ondulações de baixa frequência presentes nas tensões dos capacitores. Ainda, é proposta uma estratégia de modulação vetorial para conversores com diodos de grampeamento de três níveis em configuração back-toback com o propósito de conectar sistemas de geração eólica à rede. Nesta estratégia de modulação é combinada a utilização dos diagramas vetoriais N3V e NS3V para ambos os conversores conectados ao mesmo barramento CC. Dessa forma é possível estabelecer um compromisso entre ondulação das tensões dos capacitores do barramento CC e THD das tensões de saída. Resultados experimentais e análises comparativas são apresentadas e demonstram a boa performance dos métodos propostos.

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The high penetration of renewable energy and the emerging concept of micro-grid system raises challenges to the high power conversion techniques. Multilevel converter plays the key role in such applications and is studied in detail in the dissertation. The topologies and modulation techniques for multilevel converter are categorized at first by a thorough literature survey. The pros and cons for various multilevel topologies and modulation techniques are discussed. The 3-level neutral point clamped (NPC) topology is selected to build a 200kVA, 20 kHz power conversion system. The modularized phase leg building block of the converter is carefully designed to achieve low loss and stress for high frequency and high power operation. The switching characteristics for all the commutation loops of 3-level phase leg are evaluated by double pulse tests. The switching performance is optimized for loss and stress tradeoff. A detailed loss model is built for system loss distribution and loss breakdown calculation. Loss and stress for the phase leg and 3-phase system are quantified at all power factors. The space vector modulation (SVM) for 3-level NPC converter is investigated to achieve loss reduction, neutral voltage balance and noise reduction. The loss model and simulation model provides a quantitative analysis for loss and neutral voltage ripple tradeoff. An improved SVM method is proposed to reduce NP imbalance and switching loss simultaneously. This method also ensures an evenly distributed device loss in each phase leg and gives a constant system efficiency under different power factors. Based on the improved modulation strategy, a new modulation scheme is then proposed with largely reduced conduction loss and switching stress. Moreover, the device loss and stress distribution on a phase leg is more even. This scheme also features on the simplified implementation. The improved switching characteristics for the proposed method are verified by double pulse tests. Also the system loss breakdown and the phase leg loss distribution analysis shows the loss reduction and redistribution result. The harmonic filter for the grid interface converter is designed with LCL topology. A detailed inductor current ripple analysis derives the maximum inductor current ripple and the ripple distribution in a line cycle. The inverter side inductor is designed with the optimum loss and size trade-off. The grid side inductor is designed based on grid code attenuation requirement. Different damping circuits for LCL filter are evaluated in detail. The filter design is verified by both simulation and hardware experiment. The average model for the 3-level NPC converter and its equivalent circuit is derived with the consideration of damping circuit in both ABC and d-q frame. The modeling and control loop design is verified by transfer function measurement on real hardware. The control loops design is also tested and verified on real hardware. The interleaved DC/DC chopper is introduced at last. The different interleaving methods and their current ripple are analyzed in detail with the coupled and non-coupled inductor. An integrated coupled inductor based on 3-dimentional core structure is proposed to achieve high power density and provide both CM and DM impedance for the inductor current and output current. / Ph. D.