The presented dissertation thesis deals with modular design of analog circuits in CMOS technology. The goal of the work is to design a set of modular microelectronic building blocks and realize the selected modern active circuits, working primarily in current mode. Nevertheless, the modular approach can be used for design of generally known classical elements, e.g. opamps, as well. As a part of the work, the development of the totally new highly versatile active circuit CCTA has been done, including detailed analysis of utilization and introduction of the most interesting applications. This circuit CCTA, together with relative, already theoretically treated circuit CDTA, has been realized here for the first time, in two different topologies. Final circuits were tested. On the basis of measurement results the library of behavioral models for PSpice was created, including exemplary simulations of the selected applications. Based on the obtained knowledge the brief comparison of voltage mode circuits and current mode circuits was done.

<p>Nisko-šumni pojačavač (NŠP) nalazi se u prijemnom delu bežičnog<br />primopredajnika neposredno nakon antene. NJegova uloga je da ulazni<br />signal određene frekvencije i male snage izdvoji i pojača iznad nivoa<br />šuma prijemnika. U okviru doktorske disertacije prikazane su i<br />opisane metode za projektovanje širokopojasnih (UWB) NŠP u CMOS<br />tehnologiji. Ukupno je predloženo devet novih konfiguracija NŠP. Na<br />osnovu dobijenih rezultata, u 0,18 &mu;m UMC CMOS tehnologiji<br />realizovan je i fabrikovan NŠP jednostavne topologije, koja<br />predstavlja zbir dva pristupa, pojačavačkog stepena kaskodne<br />strukture sa povratnom spregom i stepena sa višestrukim<br />iskorišćenjem struje. NŠP je projektovan za frekvencijski opseg od<br />3,1 do 5 GHz. Takođe, opisana je metoda za merenje parametara NŠP, a<br />zatim je i izvršena njegova karakterizacija.</p> / <p>In the transceiver chain the low noise amplifier (LNA) is placed in the frontend<br />of the receiver after the antenna. The LNA needs to isolate and amplify<br />received weak signal at a specific frequency above the noise level of the<br />receiver. In the scope of this doctoral dissertation methods for designing<br />ultra-wideband (UWB) LNA in CMOS technology are presented and<br />described. Nine new LNA configurations were proposed. Based on the<br />obtained results, simple LNA configuration, obtained by merging casode<br />feedback topology and current-reuse technique, was realized and fabricated<br />in 0.18 &mu;m UMC CMOS technology. The LNA is designed for the frequency<br />band from 3.1 to 5 GHz. In addition, the method for measurement LNA<br />parameters is described and the proposed LNA was characterized.</p>

L’objectif des travaux menés dans le cadre de cette thèse est le déploiement d’un dispositif médical embarqué et portable assurant l’acquisition et la transmission du signal biomédical électrocardiogramme. Il doit intégrer des techniques de traitement avancées et un étage de communication radio. A la quête de nouvelles idées non encore explorées par la communauté scientifique, nous proposons dans notre travail d’appliquer une acquisition compressée intelligente par exploitation du caractère parcimonieux du signal électrocardiogramme à l’aide d’un convertisseur analogique-numérique à échantillonnage non-uniforme. / The objective of this thesis is the deployment of an embedded and portable medical device for acquisition and transmission of the biomedical electrocardiogram signal. The device incorporates advanced processing techniques and a radio communication module. In search of new ideas not yet explored by the scientific community, we propose in our work to apply an intelligent compressed acquisition by exploiting the sparsity character of the electrocardiogram using a non-uniform sampling analog-to-digital converter.

Ion sensing represents a grand research challenge. It finds a vast variety of applications in, e.g., gas sensing for domestic gases and ion detection in electrolytes for chemical-biological-medical monitoring. Semiconductor genome sequencing exemplifies a revolutionary application of the latter. For such sensing applications, the signal mostly spans in the low frequency regime. Therefore, low-frequency noise (LFN) present in the same frequency domain places a limit on the minimum detectable variation of the sensing signal and constitutes a major research and development objective of ion sensing devices. This thesis focuses on understanding LFN in ion sensing based on both experimental and theoretical studies. The thesis starts with demonstrating a novel device concept, i.e., ion-gated bipolar amplifier (IGBA), aiming at boosting the signal for mitigating the interference by external noise. An IGBA device consists of a modified ion-sensitive field-effect transistors (ISFET) intimately integrated with a bipolar junction transistor as the internal current amplifier with an achieved internal amplification of 70. The efficacy of IGBA in suppressing the external interference is clearly demonstrated by comparing its noise performance to that of the ISFET counterpart. Among the various noise sources of an ISFET, the solid/liquid interfacial noise is poorly studied. A differential microelectrode cell is developed for characterizing this noise component by employing potentiometry and electrochemical impedance spectroscopy. With the cell, the measured noise of the TiN/electrolyte interface is found to be of thermal nature. The interfacial noise is further found to be comparable or larger than that of the state-of-the-art MOSFETs. Therefore, its influence cannot be overlooked for design of future ion sensors. To understand the solid/liquid interfacial noise, an electrochemical impedance model is developed based on the dynamic site-binding reactions of surface hydrogen ions with surface OH groups. The model incorporates both thermodynamic and kinetic properties of the binding reactions. By considering the distributed nature of the reaction energy barriers, the model can interpret the interfacial impedance with a constant-phase-element behavior. Since the model directly correlates the interfacial noise to the properties of the sensing surface, the dependencies of noise on the reaction rate constants and binding site density are systematically investigated.

Ce travail s’inscrit dans un projet consistant à développer un prototype de capteur RF autonome et intelligent permettant la réalisation d’un réseau de capteurs sans fil dans un environnement industriel. Cette thèse traite de l’étude, la conception et la réalisation de la partie radiofréquence de la chaîne d’émission sans fils du capteur RF dans la bande ISM 863-870 MHz en technologie CMOS AMS 0.35µm. Cette chaîne inclut toutes les fonctions depuis l’oscillateur local jusqu’à l’amplificateur de puissance. L’émetteur occupe une surface de 0.22mm² et consomme environ 27mA sous une tension d’alimentation de 3.3V. De nombreux principes innovants ont été mis en œuvre et validés. Tous ces principes peuvent être facilement transposés à d’autres standards de communication et dans d’autres bandes de fréquences. Les résultats de simulations du dessin des masques vérifient complètement les spécifications et confirment les simulations. Une caractérisation expérimentale partielle valide les nouvelles architectures proposées. / This work joins in a project consisting in developing prototype of an autonomous and smart RF sensor allowing the realization of a wireless sensor network in an industrial environment. This thesis deals with the study, the design and the realization of the radio-frequency part of the transmitter using the 863-870 MHz ISM band and the CMOS AMS 0.35µm technology. This transmitter includes all the functions from the local oscillator to the power amplifier. The integrated circuit occupies a surface of 0.22mm² and consumes approximately 27mA under a supply voltage of 3.3V. Numerous innovative principles were implemented and validated. All these principles can be easily transposed into other standards of communication and in other frequency bands. The results of the post-layout simulation completely satisfy the specifications and confirm the simulations. Partial experimental characterization validates new architectures proposed.

O desenvolvimento deste trabalho foi motivado pela alta demanda de novas aplicações para o mercado do consumidor que necessitam de sistemas de transmissão e recepção de dados sem fio trabalhando na região de ondas milimétricas (mmW - entre 30 GHz e 300 GHz). Para estes tipos de sistemas, os defasadores são cruciais por definir o custo e o tamanho do dispositivo final. A pesquisa bibliográfica mostra que a melhor opção são os defasadores passivos do tipo linha carregada que utilizam Sistemas Microeletromecânicos (MEMS) como elemento de ajuste para a mudança de fase. Por esse motivo neste trabalho foi feito o estudo de diferentes tecnologias para o desenvolvimento de defasadores baseados em MEMS distribuídos e linhas de transmissão com efeito de ondas lentas de tipo shielded-CoPlanar Stripline (S-CPS) e shielded-Coplanar Waveguide (S-CPW). Foram estudadas três diferentes tecnologias: a tecnologia CMOS; a tecnologia dedicada desenvolvida pelo Laboratoire d\'électronique des technologies de l\'information (CEA-Leti) e a tecnologia in-house desenvolvida no Laboratório de Microeletrônica da Universidade de São Paulo. Utilizando a tecnologia CMOS foram fabricadas linhas de transmissão de tipo S-CPS utilizando a tecnologia de 250 nm da IHP (Innovations for High Performance Microelectronics) e a tecnologia de 0,35 µm da AMS (Austria Micro Systems). A tecnologia de 0,35 µm da AMS foi utilizada também para o desenvolvimento de defasadores de 2-bits e 3-bits baseados em linhas de transmissão de tipo S-CPW. Para estes defasadores foi definido um processo de liberação da camada de blindagem, reprodutível, que permitiu a atuação do dispositivo. Outros defasadores baseados em S-CPW que foram desenvolvidos anteriormente com a tecnologia dedicada CEA-LETI, foram modelados eletrostaticamente utilizando o Comsol MultiPhysics e o Ansys Workbench. Os modelos desenvolvidos permitiram entender o comportamento eletromecânico do defasador e foram utilizados reprojetar o defasador com um desempenho otimizado. Finalmente, visando o desenvolvimento dos dispositivos otimizados utilizando a tecnologia in house com os materiais e métodos disponíveis no Laboratório de Microeletrônica da USP (LME-USP), foram estudadas algumas etapas críticas do processo de fabricação. / The development of this work is motivated by the high demand for new applications for the consumer market that require wireless systems for data transmission and reception working in the millimeter wave region (mmW - between 30 GHz and 300 GHz). For these kinds of systems, the phase shifter are crucial to define the cost and size of the final device. The bibliographical research shows that the best option are the passive load line-type phase shifters using Microelectromechanical Systems (MEMS) as tuning element. Therefore, in this work, the study of different technologies for the development of phase shifter based on distributed MEMS and slow-wave transmission lines. The two types of transmission lines considered were the shielded-CoPlanar Stripline (S-CPS) and shielded-Coplanar Waveguide line (S-CPW). Three different technologies were studied: CMOS technology; the dedicated technology developed by the Laboratoire d\'électronique des technologies de l\'information (CEA-Leti) and the in-house technology developed at the Microelectronics Laboratory of the University of São Paulo. Using the CMOS technology, S-CPS-type transmission lines were fabricated using IHP\'s 250 nm CMOS technology and AMS\'s 0.35 µm CMOS technology. AMS\'s 0.35 µm technology has also been used for the development of 2-bit and 3-bit phase-shifters based on S-CPW type transmission lines. For these phase shifters, a reproducible shielding layer release process was defined that allowed the device to operate. Also, another phase shifter based in S-CPW-type transmission lines that were previously developed with dedicated CEA-LETI technology was electrostatically modeled using Comsol MultiPhysics and Ansys Workbench. The developed models allowed to understand the electromechanical behavior of the phase shifter and was used for a new design of the phase shifter with an optimized performance. Finally, in order to develop the optimized devices using the in-house technology with the materials and methods available at the USP Microelectronics Laboratory (LME-USP), some critical stages of the fabrication process were studied.

Les objectifs de la thèse concernent l’optimisation du rendement énergétique, la minimisation de l’empreinte et du coût de l’alimentation en tension d’amplificateurs audio pour l’application casque des plateformes mobiles. Après une présentation du contexte des plateformes mobiles et des caractéristiques principales des amplificateurs audio dédiés, l’introduction conclut sur la nécessité d’une alimentation en tensions bipolaires, symétriques et donne les spécifications principales d’une telle alimentation en énergie électrique. Le chapitre d’état de l’art présente dans un premier temps les architeture les plus compétitves permettant de générer deux tensions symétriques. Une figure de mérite englobe le rendement énergétique, l’empreinte sur la plateforme et le coût en composants passifs externes de chacune des solutions présentées. Une architecture de convertisseur utilisant une seule inductance pour obtenir des tensions régulées symétriques se révelle etre un candidat interessant pour l’alimentation des amplificateurs dédiés aux casques audio. Cette architecture à été démontrée mais cependant loin des spécifications de l’application casque audio. Basée sur cette architecture, le chapitre troisième présente un étage de puissance et ses modes de conduction correspondant aux spécifications de l’application casque audio. Des détails concernent en particulier la conception des interrupteurs ainsi que la stratégie d’asservissement et de régulation. Des premières estimations de rendement sont évaluées dans les pires cas de fonctionnement. Très tôt dans le déroulement de la thèse, il y a eu une opportunité de tester l’étage de puissance en technologie CMOS 130nm. Le chapitre 4 présente l’implémentation du convertisseur sur un circuit de test. Le convertisseur est embarqué notamment à côté d’un amplificateur audio dédié, autorisant des tests plus proches de la réalité d’usage. Les campagnes de mesures ont concerné les aspects fonctionnels et les valeurs de rendement. Les résultats sont encourageants mais confirment les éléments non optimaux du dispositif. Dans l’idée d’un second silicium, le chapitre cinquième décrit plus théoriquement l’approche d’asservissement et de régulation et met en évidence des cas critiques, peu probables mais concrets, liés à l’évaluation sur des profils de charge réelle du convertisseur. Des simulations permettent de transformer un flux audio en courbe de courant absorbé par l’amplificateur audio, c’est-à-dire la charge réelle vue par le convertisseur de tensions symétriques. Le chapitre sixième décrit des améliorations à propos des modes de conduction, à savoir l’introduction des modes discontinu ou d’élimination d’impulsion (pulse skipping). Malheureusement une crise économique a barré l’accès à un silicium de validation finale. Le manuscrit est conclu par un rappel des résultats principaux et des perspectives. Les travaux ont fait l’objet de publications à des conférences internationales. / The objectives of this thesis were the optimization of the power efficiency and the minimization of the footprint area and cost of the integrated power supply of headset audio amplifiers on mobile platforms (fig. 1). The thesis took place in the Analog System Design group at ST Ericsson in strong collaboration with Ampere laboratory at INSA de Lyon. The french agency ANRT provided part of the project funding. The first chapter presents the current mobile platform context as well as the main characteristics of audio amplifiers driving headphones. This chapter concludes giving the need of a symmetrical power supply for the headset audio amplifiers and giving a set of electrical specifications for this power supply. The second chapter presents the state-of-the-art in terms of symmetrical power supply architectures able to fit the previously given characteristics and specifications. A set of key parameters based on the power efficiency, the relative silicon area, the relative external bill of material, the number of Input/Output pins and the external passive components area, is employed to benchmark all existing architectures to supply such audio amplifiers. This benchmark reveals the novel Single Inductor Bipolar Output (SIBO) converter as very promising. The similar existing circuits are also detailed and pros and cons of each one of them are discussed to define the most suited architecture. The third chapter proposes a dedicated power stage architecture and related conduction schemes. The design of the power stage is described as well as its dedicated control strategy. Some ideal efficiency estimations are given. The fourth chapter presents the realization of a first prototype, designed in a 130 nm ST Microelectronics CMOS process to be an early demonstrator of the architecture in chapter 3. Measurements on efficiency, control and transient performances are presented and discussed. This circuit embedded on the same die as an audio amplifier proves its effectiveness in supplying such a circuit. The fifth chapter presents a theoretical analysis of the feedback control of this SIBO converter. Mathematical linear model of the converter is derived to obtain its transfer function matrix, then the feedback structure design is defined thanks to dedicated mathematical tools. A set of classical PID controllers is proposed and validated with piecewise linear model while playing different audio popular songs. The sixth chapter describes the design of improvements of the first test chip as well as simulation results about these improvements. The main improvements presented in this chapter are a Discontinuous Conduction Mode (DCM) as well as a Pulse Skipping Mode (PSM). No silicon result can be presented here due to a budget restriction that impacted the course of the thesis. The final chapter is a discussion about the proposed solutions and some perspectives to the present work.

O desenvolvimento deste trabalho foi motivado pela alta demanda de novas aplicações para o mercado do consumidor que necessitam de sistemas de transmissão e recepção de dados sem fio trabalhando na região de ondas milimétricas (mmW - entre 30 GHz e 300 GHz). Para estes tipos de sistemas, os defasadores são cruciais por definir o custo e o tamanho do dispositivo final. A pesquisa bibliográfica mostra que a melhor opção são os defasadores passivos do tipo linha carregada que utilizam Sistemas Microeletromecânicos (MEMS) como elemento de ajuste para a mudança de fase. Por esse motivo neste trabalho foi feito o estudo de diferentes tecnologias para o desenvolvimento de defasadores baseados em MEMS distribuídos e linhas de transmissão com efeito de ondas lentas de tipo shielded-CoPlanar Stripline (S-CPS) e shielded-Coplanar Waveguide (S-CPW). Foram estudadas três diferentes tecnologias: a tecnologia CMOS; a tecnologia dedicada desenvolvida pelo Laboratoire d\'électronique des technologies de l\'information (CEA-Leti) e a tecnologia in-house desenvolvida no Laboratório de Microeletrônica da Universidade de São Paulo. Utilizando a tecnologia CMOS foram fabricadas linhas de transmissão de tipo S-CPS utilizando a tecnologia de 250 nm da IHP (Innovations for High Performance Microelectronics) e a tecnologia de 0,35 µm da AMS (Austria Micro Systems). A tecnologia de 0,35 µm da AMS foi utilizada também para o desenvolvimento de defasadores de 2-bits e 3-bits baseados em linhas de transmissão de tipo S-CPW. Para estes defasadores foi definido um processo de liberação da camada de blindagem, reprodutível, que permitiu a atuação do dispositivo. Outros defasadores baseados em S-CPW que foram desenvolvidos anteriormente com a tecnologia dedicada CEA-LETI, foram modelados eletrostaticamente utilizando o Comsol MultiPhysics e o Ansys Workbench. Os modelos desenvolvidos permitiram entender o comportamento eletromecânico do defasador e foram utilizados reprojetar o defasador com um desempenho otimizado. Finalmente, visando o desenvolvimento dos dispositivos otimizados utilizando a tecnologia in house com os materiais e métodos disponíveis no Laboratório de Microeletrônica da USP (LME-USP), foram estudadas algumas etapas críticas do processo de fabricação. / The development of this work is motivated by the high demand for new applications for the consumer market that require wireless systems for data transmission and reception working in the millimeter wave region (mmW - between 30 GHz and 300 GHz). For these kinds of systems, the phase shifter are crucial to define the cost and size of the final device. The bibliographical research shows that the best option are the passive load line-type phase shifters using Microelectromechanical Systems (MEMS) as tuning element. Therefore, in this work, the study of different technologies for the development of phase shifter based on distributed MEMS and slow-wave transmission lines. The two types of transmission lines considered were the shielded-CoPlanar Stripline (S-CPS) and shielded-Coplanar Waveguide line (S-CPW). Three different technologies were studied: CMOS technology; the dedicated technology developed by the Laboratoire d\'électronique des technologies de l\'information (CEA-Leti) and the in-house technology developed at the Microelectronics Laboratory of the University of São Paulo. Using the CMOS technology, S-CPS-type transmission lines were fabricated using IHP\'s 250 nm CMOS technology and AMS\'s 0.35 µm CMOS technology. AMS\'s 0.35 µm technology has also been used for the development of 2-bit and 3-bit phase-shifters based on S-CPW type transmission lines. For these phase shifters, a reproducible shielding layer release process was defined that allowed the device to operate. Also, another phase shifter based in S-CPW-type transmission lines that were previously developed with dedicated CEA-LETI technology was electrostatically modeled using Comsol MultiPhysics and Ansys Workbench. The developed models allowed to understand the electromechanical behavior of the phase shifter and was used for a new design of the phase shifter with an optimized performance. Finally, in order to develop the optimized devices using the in-house technology with the materials and methods available at the USP Microelectronics Laboratory (LME-USP), some critical stages of the fabrication process were studied.

The presented dissertation thesis deals with a novel structure of delta-sigma () modulator which compensates influence of higher harmonic distortion and therefore it is possible to achieve high resolution up to 16 bits. This novel proposed structure combines advantages of one bit quantizer modulators with mutli-bit modulators. The novel second order structure is presented, correct function is verified in MATLAB simulation enviroment and requirements for partial block are studied. The second part of the work deals with design of converter with novel structure of modulator using switched capacitor technique utilizing ONSemi I3T25 technology. Advantages and disadvantages of the novel structure are evaluated and novel structure is compared with common structures of modulators.

Speed, power and reliability of analogue integrated circuits (IC) exhibit temperature dependency through the modulation of one or several of the following variables: band gap energy of the semiconductor, mobility, carrier diffusion, current density, threshold voltage, interconnect resistance, and variability in passive components. Some of the adverse effects of temperature variations are observed in current and voltage reference circuits, and frequency drift in oscillators. Thermal instability of a voltage-controlled oscillator (VCO) is a critical design factor for radio frequency ICs, such as transceiver circuits in communication networks, data link protocols, medical wireless sensor networks and microelectromechanical resonators. For example, frequency drift in a transceiver system results in severe inter-symbol interference in a digital communications system. Minimum transconductance required to sustain oscillation is specified by Barkhausen’s stability criterion. However it is common practice to design oscillators with much more transconductance enabling self-startup. As temperature is increased, several of the variables mentioned induce additional transconductance to the oscillator. This in turn translates to a negative frequency drift. Conventional approaches in temperature compensation involve temperature-insensitive biasing proportional-to-absolute temperature, modifying the control voltage terminal of the VCO using an appropriately generated voltage. Improved frequency stability is reported when compensation voltage closely follows the frequency drift profile of the VCO. However, several published articles link the close association between oscillation amplitude and oscillation frequency. To the knowledge of this author, few published journal articles have focused on amplitude control techniques to reduce frequency drift. This dissertation focuses on reducing the frequency drift resulting from temperature variations based on amplitude control. A corresponding hypothesis is formulated, where the research outcome proposes improved frequency stability in response to temperature variations. In order to validate this principle, a temperature compensated VCO is designed in schematic and in layout, verified using a simulation program with integrated circuit emphasis tool using the corresponding process design kit provided by the foundry, and prototyped using standard complementary metal oxide semiconductor technology. Periodic steady state (PSS) analysis is performed using the open loop VCO with temperature as the parametric variable in five equal intervals from 0 – 125 °C. A consistent negative frequency shift is observed in every temperature interval (≈ 11 MHz), with an overall frequency drift of 57 MHz. However similar PSS analysis performed using a VCO in the temperature stabilised loop demonstrates a reduced negative frequency drift of 3.8 MHz in the first temperature interval. During the remaining temperature intervals the closed loop action of the amplitude control loop overcompensates for the negative frequency drift, resulting in an overall frequency spread of 4.8 MHz. The negative frequency drift in the first temperature interval of 0 to 25 °C is due to the fact that amplitude control is not fully effective, as the oscillation amplitude is still building up. Using the temperature stabilised loop, the overall frequency stability has improved to 16 parts per million (ppm)/°C from an uncompensated value of 189 ppm/°C. The results obtained are critically evaluated and conclusions are drawn. Temperature stabilised VCOs are applicable in applications or technologies such as high speed-universal serial bus, serial advanced technology attachment where frequency stability requirements are less stringent. The implications of this study for the existing body of knowledge are that better temperature compensation can be obtained if any of the conventional compensation schemes is preceded by amplitude control. / Dissertation (MEng)--University of Pretoria, 2013. / Electrical, Electronic and Computer Engineering / unrestricted