Field Programmable Gate Arrays (FPGAs) are a reconfigurable hardware platform which enable the acceleration of software code through the use of custom-hardware circuits. Complex systems combining processors with programmable logic require partitioning to decide which code segments to accelerate. This thesis provides tools to help determine which software code sections would most benefit from hardware acceleration. A low-overhead profiling architecture, called LEAP, is proposed to attain real-time profiles of an FPGA-based processor. LEAP is designed to be extensible for a variety of profiling tasks, three of which are investigated and implemented to identify candidate software for acceleration. 1) Cycle profiling determines the most time-consuming functions to maximize speedup. 2) Cache stall profiling detects memory-intensive code; large memory overheads reduce the benefits of acceleration. 3) Energy consumption profiling detects energy-inefficient code through the use of an instruction-level power database to minimize the system's energy consumption.

A hardware implementation can bring orders of magnitude improvements in performance and energy consumption over a software implementation. Hardware design, however, can be extremely difficult. High-level synthesis, the process of compiling software to hardware, promises to make hardware design easier. However, compiling an entire software program to hardware can be inefficient. This thesis proposes hardware/software co-design, where computationally intensive functions are accelerated by hardware, while remaining program segments execute in software. The work in this thesis builds a framework where user-designated software functions are automatically compiled to hardware accelerators, which can execute serially or in parallel to work in tandem with a processor. To support multiple parallel accelerators, new multi-ported cache designs are presented. These caches provide low-latency high-bandwidth data to further improve the performance of accelerators. An extensive range of cache architectures are explored, and results show that certain cache architectures significantly outperform others in a processor/accelerator system.

Co-design is a process that allows designers to develop products with greater insight to user needs through the participation of users in the design process. During this process what users say, make, and do is investigated using common research methods in combination with newer generative and exploratory approaches created for this purpose. Co-design encompasses many design practices. Despite the prevalence of the co-design process, a lack of studies into the education of designers on co-design have been implemented, leaving a gap of information that needs to be filled in order for co-design to become integrated into design education and practice. The purpose of this project is to understand the current state of co-design education in the U.S. and to assimilate popular teaching techniques, by surveying teaching methods of co-design within Industrial Design programs at U.S. Universities with reputations as leaders in the field. This project also aims to design a learning aid for Industrial Design students derived from the findings of interviews, materials review, and literature. A snowball sampling was performed with schools leaders in co-design. Schools were contacted and given a survey, interviewed with selected participants and assessed on their materials and practices on co-design. Various qualitative data analysis was performed with the surveys, interviews and materials. The conclusion includes a composite of common methods for teaching co-design, which are assembled into a learning aid artifact. The artifact incorporates findings into a practical outcome. The significance of this project is to further research into teaching methods of co-design as well as providing a common framework for design educators to follow in higher level learning institutions.

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Medical devices processing images or audio or executing complex AI algorithms are able to run more efficiently and meet real time requirements if the parallelism in those algorithms is exploited. In this research a methodology is proposed to exploit the flexibility and short design cycle of FPGAs (Field Programmable Gate Arrays) in order to achieve this target. Hardware/software co-design and dynamic partitioning allow the optimization of the multiprocessor platform design parameters and software code targeting each core to meet real time constraints. This is practically demonstrated by building a real life driver vigilance monitoring system based on visual cues extraction and evaluation. The application drives the whole design process to prove its effectiveness. An algorithm was built to achieve the goal of detecting the eye state of the driver (open or closed) and it is applied on captured consecutive frames to evaluate the vigilance state of the driver. Vigilance state is measured depending on duration of eye closure. This video processing application is then targeted to run on a multi-core FPGA based processing platform using the proposed methodology. Results obtained were very good using the Grimace Face Database and when operating the system on one’s face. On operating the device, a false positive of eye closure must take place two consecutive times in order to get an alarm, which decreases the probability of failure. The timing analysis applied proved the importance of using the concept of parallelism to achieve performance constraints. FPGA technology proved to be a very powerful prototyping tool for complex multiprocessor systems design. The flexible FPGA technology coupled with hardware/software co-design provided means to explore the design space and reach decisions that satisfy the design constraints with minimum time investment and cost.

Background: Recent focus on quality and patient safety has underlined the need to involve patients in improving healthcare. “Experience-based Co-design” (EBCD) is an approach to capture and understand patient and staff (i. e. users) experiences, identifying so called “touch points” and then working together equally in improvement efforts. Purpose: This article elucidates patient (defined as the mother-newborn couple with next of kin) and staff experiences following improvement work carried out according to EBCD in a maternity ward and neonatal intensive care unit (NICU) in a small, acute hospital in Sweden. Method: An experience questionnaire, derived from the EBCD approach tool set, was used for continuously evaluating each event of the EBCD improvement project. Furthermore, a focus group interview with staff and in-depth interviews with mother-father couples were held in order to collect and understand the experiences of working together according to EBCD. The analysis and interpretation of the interview data was carried through using qualitative, problem-driven content analysis. Themes, categories and sub-categories presented in this study constitute the manifest and latent content of the participants’ experiences of Experience-based Co-design. Results: The analysis of the experience questionnaires, prior to the interviews, revealed mostly positive experiences of the participation. Both staff and patient participants stated generally happy, involved, safe, good and comfortable experiences following each event of the improvement project so far. Two themes emerged during the analysis of the interviews. For staff participants the improvement project was a matter of learning within the microsystem through managing practical issues, moving beyond assumptions of improvement work and gaining a new way of thinking. For patients, taking part of the improvement project was expressed as the experience of involvement in healthcare through their participation and through a sense of improving for the future. Discussion: This study confirms that, despite practical obstacles for participants, the EBCD approach to improvement work provided an opportunity for maternity ward /NICU care being explored respectfully at the experience level, by assuring the sincere sharing of useful information within the microsystem continuously, and by encouraging and supporting the equal involvement of both staff and patients. Staff and patients wanted and were able to contribute to the EBCD process of gathering information about their experiences, analyzing and responding to collected data, and engaging themselves in improving the same. Furthermore, the EBCD approach provided staff and patients the opportunity of learning within the microsystem. Nevertheless, the responsibility of the improvement work remained the responsibility of the healthcare professionals. Keywords: Quality Improvement, Maternity Care, Neonatal Intensive Care, Experience-based Co-design

Background: Recent focus on quality and patient safety has underlined the need to involve patients in improving healthcare. “Experience-based Co-design” (EBCD) is an approach to capture and understand patient and staff (i. e. users) experiences, identifying so called “touch points” and then working together equally in improvement efforts. Purpose:This article elucidates patient (defined as the mother-newborn couple with next of kin) and staff experiences following improvement work carried out according to EBCD in a maternity ward and neonatal intensive care unit (NICU) in a small, acute hospital in Sweden. Method: An experience questionnaire, derived from the EBCD approach tool set, was used for continuously evaluating each event of the EBCD improvement project. Furthermore, a focus group interview with staff and in-depth interviews with mother-father couples were held in order to collect and understand the experiences of working together according to EBCD. The analysis and interpretation of the interview data was carried through using qualitative, problem-driven content analysis. Themes, categories and sub-categories presented in this study constitute the manifest and latent content of the participants’ experiences of Experience-based Co-design. Results:The analysis of the experience questionnaires, prior to the interviews, revealed mostly positive experiences of the participation. Both staff and patient participants stated generally happy, involved, safe, good and comfortable experiences following each event of the improvement project so far. Two themes emerged during the analysis of the interviews. For staff participants the improvement project was a matter of learning within the microsystem through managing practical issues, moving beyond assumptions of improvement work and gaining a new way of thinking. For patients, taking part of the improvement project was expressed as the experience of involvement in healthcare through their participation and through a sense of improving for the future. Discussion: This study confirms that, despite practical obstacles for participants, the EBCD approach to improvement work provided an opportunity for maternity ward /NICU care being explored respectfully at the experience level, by assuring the sincere sharing of useful information within the microsystem continuously, and by encouraging and supporting the equal involvement of both staff and patients. Staff and patients wanted and were able to contribute to the EBCD process of gathering information about their experiences, analyzing and responding to collected data, and engaging themselves in improving the same. Furthermore, the EBCD approach provided staff and patients the opportunity of learning within the microsystem. Nevertheless, the responsibility of the improvement work remained the responsibility of the healthcare professionals.

Medical devices processing images or audio or executing complex AI algorithms are able to run more efficiently and meet real time requirements if the parallelism in those algorithms is exploited. In this research a methodology is proposed to exploit the flexibility and short design cycle of FPGAs (Field Programmable Gate Arrays) in order to achieve this target. Hardware/software co-design and dynamic partitioning allow the optimization of the multiprocessor platform design parameters and software code targeting each core to meet real time constraints. This is practically demonstrated by building a real life driver vigilance monitoring system based on visual cues extraction and evaluation. The application drives the whole design process to prove its effectiveness. An algorithm was built to achieve the goal of detecting the eye state of the driver (open or closed) and it is applied on captured consecutive frames to evaluate the vigilance state of the driver. Vigilance state is measured depending on duration of eye closure. This video processing application is then targeted to run on a multi-core FPGA based processing platform using the proposed methodology. Results obtained were very good using the Grimace Face Database and when operating the system on one’s face. On operating the device, a false positive of eye closure must take place two consecutive times in order to get an alarm, which decreases the probability of failure. The timing analysis applied proved the importance of using the concept of parallelism to achieve performance constraints. FPGA technology proved to be a very powerful prototyping tool for complex multiprocessor systems design. The flexible FPGA technology coupled with hardware/software co-design provided means to explore the design space and reach decisions that satisfy the design constraints with minimum time investment and cost.

In the last years, with more and more transistors can fit into a chip, the growth the IC design complexity is fast and original design flow can¡¦t cater for designers. Therefore, so many people promote to integrate the system into a single chip gradually with the last technology using the concept of hardware/software co-design. In this thesis, we use the hardware/software co-design concept to build a simple video codec from system level and implement it on the ARM¡¦s SOC platform. We focus on the hardware/software co-ordination. Because we use the platform-based design method, the build hardware/software modules can be used in the similar architecture on the ARM platform In our Video codec system, discrete wavelet transform(DWT) and RGBtoYCbCr are the most timing-consuming parts. Since DWT has inherent scalability and excellent features of energy compaction, it has been applied widely in the various image compression systems. We adopt the 5-3 filter lifting-based DWT in the hardware part of our system and design three different lifting-based DWT architectures by using the high level synthesis concept to optimize the hardware utilization and speed. In the premise of not increasing memory access times and additional processes of software, we overcome the boundary extension of DWT and verify it by means of FPGA after combining it with the RGBtoYCbCr hardware architecture. Finally, the hardware part is integrated with the other part implemented by software, we build a completely video encode system on the ARM SOC platform using the hardware/software co-design.

MP3 compression format is essential categorized one of the MPEG (Moving Picture Experts Group) standards for digital audio compression nowadays. For its superiority and convenient,MP3 has been widely used in multimedia player and storage application. In this thesis, we use software/hardware co-design methodology to design the MP3 player system. In addition, system level scheduling is adopted to arrange the execute time of SW and HW and significantly reduce the hardware cost under the construct of real-time processing. We can obtain fewer extra hardware cost while attaining the goal of real- time playing system. In order to perform software/hardware partitioning, simulate and analyze the MP3 application program to find out the critical parts with high time complexity and regular computation. These parts with high time complexity, e.g. IMDCT and Poly Phase synthesis filter bank, then are implemented by hardware to achieve better system performance. We use high level synthesis concept to optimize the hardware part and integrate software and hardware¡Asuch that communication between software and hardware can be performed smoothly. Finally, MP3 player system is using verified by hardware¡Bsoftware co- verified methodology on an SoC development platform. In order to build a complete verification environment, we attach extra input and output interfaces to the SoC development platform, e.g. the network card and sound card. Write some driver to drive related peripheral device. Since OS is conducive to the operations between software and hardware, Linux OS is ported to the SoC platform to manage software and hardware resources and drive the peripheral devices.