The topic of stereo video is getting more attention among these days due to its high quality of visual effect. However, the large volume of data is the problem of its application. There is much similarity between the parallax videos. This similarity is obtained by a shape compensation technique. The topic of this thesis is to investigate a compression technique by on the shape compensation stereo video data. The shape transformation in this paper is coded by the kinds of morphological operations to be applied. This processing is a type of operation by which the spatial form or structure of objects within an image are modified. Morphological operation is usually applied to the binary images. There are two problems for the selection of the optimal morphological filter: the collection of the candidate filters and the sources of the voters. For the gray level images the mask operation is changed to be the more complex window weighting operation. By a strategy of slicing the image umbrella, our masked gray morphological operation is also more computation-efficient than the regular gray morphological operation. Experimental results in this thesis have demonstrated that shape compensation is more efficient than motion compensation for the secondary (right) video sequence.

This thesis includes two topics. The first one is the architecture as well as the circuit implementation of an ultra low-power direct digital frequency synthesizer (DDFS) based on the straight line approximation. The second one is the circuit implementation of the low-power DDFS with an error compensation. The proposed approximation technique replaces the conventional ROM-based phase-to-amplitude conversion circuitry and the linear digital-to-analog converter with a nonlinear digital-to-analog converter (DAC) to realize a simple approximation of the sine function. Thus, the overall power dissipation as well as hardware complexity can be significantly reduced. Besides, by adding the error compensation, the spurious-free dynamic range (SFDR) of the synthesized output signal can be raised drastically.

Roller Gear Cam mechanism¡]RGC¡^has been used widely in different automation mechanisms and all kinds of orientation mechanism. High speed and high accuracy of the RGC system is a tendency in high production automation. The interaction between the driving speed and torque of a high speed RGC system is investigated in this work. The effect of adding a torque compensation cam¡]TCC¡^on the improving of indexing precision of a RGC system is investigated in this thesis. The dynamic responses of a RGC system driven by a DC motor are conducted. Dynamic equations of the intermittent- motion of a RGC driven system are derived by using the Lagrange¡¦s equation with the assumption of dual-stiffness. Furthermore, the effect of adding a torque compensation mechanism¡]TCM¡^ such as torque compensation cam¡]TCC¡^ or idle wheel on the improving of indexing precision of a RGC system is investigated in this work. The sixth order Runge-Kutta iteration method is employed in the system¡¦s responses simulation. Variations of the driving torque, driving speed and residual vibration of a RGC system with different torque compensation devices are analyzed in this research. The simulated and measured results indicate that a RGC system attached with a TCC can improve its speed and torque fluctuation at the designed speed significantly. However, this compensation effect is quite sensitive to the driving speed. On the contrary, the compensation effect introduced by using an idle wheel is not so sensitive to the speed as the TCC does. The low cost and easy design are also the favorable factors for using an idle wheel to instead of an expensive TCC device.

In recent years, the internet has been in widespread use and the number of internet subscribers increased quickly. Hence a lot of applications on the network have been developed, multimedia programs especially. Whereas the original video content always takes up considerable storage and transmission time which doesn¡¦t suit for network application, many video compression standards have been drawn up in the literature Due to the temporal redundancy of the video sequences, motion estimation / compensation has been widely used in many interframe video coding protocols to reduce the required bit rates for transmission and storage of video signals by eliminating it, such as the MPEG-1, MPEG-2, H.261 and H.263. The performance and speed of the interframe motion estimation method for video sequence compression are the important issues especially in networking application such as video conference and video on demand. Today all motion estimating method find out the estimating point which has minimal Mean Square Error, and motion compensation aim at estimating error to do JPEG. compression. As everyone knows, JPEG employs DCT to eliminate the correlation of spatial domain. So the best motion estimating point is the point which has the minimal compressed data size. In some alalyses show that over 50% best estimating point do not have the minimal compressed data size. So the factor which effects the compressed data size is correlation coefficient and not MSE. Hence, we try to define a new criterion for motion estimation which can get better motion compensation with less compressing bit rate. To reach this goal, we try to find out the correlation among the motion compensation as the new criterion for motion estimation.

The currently used DSL splitters or filters are designed for ADSL band up to 1104 KHz and ADSL2+ band up to 2208 KHz. To meet faster internet access, DSL technology has evolved from ADSL into VDSL2 with an operating band up to 30 MHz. However, the splitters in VDSL2 band have some design difficulties in longitudinal conversion loss and isolation. The main purpose of this thesis is to find some solutions to overcome these design difficulties for splitters operating in VDSL2 band. The proposed solutions include the use of common-mode choke and compensation circuit. The final testing results of the splitters can validate the proposed solutions.

Recently, multimedia applications are used widely in many embedded and portable systems, such as mobile phones, MP3 player and PDA, which require lower power consumption within high performance constraints. Therefore, power-efficient design becomes a more important objective in Very Large Scale Integration (VLSI) designs. Moreover, the multiplication unit always lies on the critical path and ultimately determines the performance and power consumption of arithmetic computing systems. To achieve high-performance and lengthen the battery lifetime, it is crucial to develop a multiplier with high-speed and low power consumption. In multimedia and digital signal processing (DSP) applications, many low-power approaches have been presented to lessen the power consumption of multipliers by eliminating spurious computations. Moreover, the multiplication operations adopted in these systems usually allow accuracy loss to output data so as to achieve more power savings. Based on these conceptions, this dissertation considers input data characteristics and the arithmetic features of multiplications in various multimedia and DSP applications and presents novel power reduction and truncation techniques to design power-efficient multipliers and high-accuracy fixed-width multipliers. In the design of array and tree multipliers, we first propose a low power pipelined truncated multiplier which dynamically deactivates non-effective circuitry based on input range. Moreover, the proposed multiplier offers a flexible tradeoff between power reduction and product precision. This reconfigurable characteristic is very useful to systems which have different requirement on output precision. Second, a low-power configurable Booth multiplier that supports several multiplication modes and eliminates the redundant computations of sign bits in multipliers as much as possible is developed. This architecture can efficaciously decrease the power consumption of systems which demand computing performance and flexibility simultaneously. Although these two kinds of low power multipliers can achieve significant power savings, the hardware complexity of error compensation circuits and error performance in terms of the mean error and mean-square error are unsuitable for many multimedia systems composed of a large amount of multiply-accumulate operations. To efficiently improve the accuracy with less hardware complexity, we propose new error compensation circuits for fixed-width tree multipliers and fixed-width modified Booth multipliers. In the design of floating-point multipliers, we propose a low power variable-latency floating-point multiplier which is compliant with IEEE 754-1985 and suitable for 3-D graphics and multimedia applications. In the architecture, the significand multiplier is first partitioned into the upper and lower parts. Next, an efficient prediction scheme for the carry bit, sticky bit, and the upper part of significand product is developed. While the correct prediction occurs, the computation of lower part of significand multiplier is shut down and therefore the floating-point multiplication can consume less power and be completed early. In the design of modular multipliers, we propose an efficient modular multiplication algorithm to devise a high performance and low power modular multiplier. The proposed algorithm adopts the quotient pipelining and superfluous-operation elimination technique to discard the data dependency and redundant computational cycles of radix-2 Montgomery¡¦s multiplication algorithm so that the operation speed, power dissipation, and energy consumption of modular multipliers can be significantly improved.

Texte remanié de: Th. doct.--Droit--Paris 9, 2001. / Bibliogr. p. 349-359. Index.

Thesis (Ph. D.)--University of Hong Kong, 2010. / Includes bibliographical references (p. 125-129). Also available in print.

Thesis (M.B.A.)--University of Hong Kong, 1985.

CEO pay-performance relationship is a topic that has been largely discussed and researched. Questions still remain on precisely how CEO remuneration is related to company performance. Recently, attention has shifted from how much executives are paid to how they are paid. The purpose of this paper is to find how CEO compensation structure relates to company performance in the auto industry. In order to achieve this aim, the CEO compensation is broken down into four components, namely: base salary, bonus, stocks and stock options, and pension. The company performance is measured by change in market value, since market information is forward looking, meaning future performance might be anticipated in advance by the markets. As such, decisions made whose positive or negative effects may occur later in the future are, if known by investors, priced into the market value. Each compensation component relative the total was tested for correlation with respective market capitalization change. However, the insignificant statistical results conclude that the compensation structure follows a relatively random pattern. Hence, no statistically significant relationship between CEO compensation structure and firm performance in the auto industry was found. The findings that there are no significant performance improvements for firms having a relatively bigger proportion of performance-based pay means that underlying theories, such as agency theory, may not be applicable in the industry.