Les applications multimédia se composent généralement de blocs numériques exhibant des schémas de calcul flottant réguliers. Sur les processeurs sans support architectural pour l'arithmétique flottante, ils peuvent être profitablement transformés en opérateurs dédiés, s'ajoutant aux 5 opérateurs élémentaires (+, -, X, / et √) : en traitant plus d'opérations simultanément, ils permettent d'obtenir de meilleures performances. Cette thèse porte sur la conception de tels opérateurs, et les techniques de compilation mises en œuvre pour les sélectionner. Nous avons réalisé des implémentations optimisées pour un ensemble d'opérateurs dédiés : élévation au carré, mise à l'échelle, fused multiply-add, produit scalaire en dimension deux (DP2), addition/soustraction simultané et sinus/cosinus simultanés. En proposant de nouveaux algorithmes cherchant à maximiser le parallélisme d'instructions et détaillés ici, nous obtenons des accélérations d'un facteur allant jusqu'à 4.2 par appel. Nous détaillons également les changements apportés dans le compilateur pour effectuer la sélection. La plupart des opérateurs sont sélectionnés au niveau syntaxique. Cependant, pour certains opérateurs, nous avons dû améliorer l'analyse d'intervalles entiers pour prendre en compte les variables de type flottant, afin de prouver certaines conditions de positivité requises à leur sélection. Enfin, nous apportons la preuve en pratique de la pertinence de cette approche : sur des noyaux typiques du traitement du signal et sur certaines applications, nous mesurons une amélioration de performance allant jusqu'à 1.59x en comparaison avec la performance obtenue avec les seuls opérateurs élémentaires. / Media processing applications typically involve numerical blocks that exhibit regular floating-point computation patterns. For processors whose architecture supports only integer arithmetic, these patterns can be profitably turned into custom operators, coming in addition to the five basic ones (+, -, X, / and √), but achieving better performance by treating more operations. This thesis addresses the design of such custom operators as well as the techniques developed in the compiler to select them in application codes. We have designed optimized implementations for a set of custom operators which includes squaring, scaling, adding two nonnegative terms, fused multiply-add, fused square-add (x*x+z, with z>=0), two-dimensional dot products (DP2), sums of two squares, as well as simultaneous addition/subtraction and sine/cosine. With novel algorithms targeting high instruction-level parallelism and detailed here for squaring, scaling, DP2, and sin/cos, we achieve speedups of up to 4.2x for individual custom operators even when subnormal numbers are fully supported. Furthermore, we introduce the optimizations developed in the ST231 C/C++ compiler for selecting such operators. Most of the selections are achieved at high level, using syntactic criteria. However, for fused square-add, we also enhance the framework of integer range analysis to support floating-point variables in order to prove the required positivity condition z>= 0. Finally, we provide quantitative evidence of the benefits to support this selection of custom operations: on DSP kernels and benchmarks, our approach allows us to be up to 1.59x faster compared to the sole usage of basic ones.

Technological advances drive hardware to ever smaller feature sizes, causing devices to become more vulnerable to transient faults. Applications can be protected against faults by adding error detection and recovery measures in software. This is popularly achieved by applying automatic program transformations. However, transformations applied to program representations at abstraction levels higher than machine instructions are fundamentally incapable of protecting against vulnerabilities that are introduced during compilation. In particular, a large proportion of a program’s memory accesses are introduced by the compiler backend. This report presents a backend that protects these accesses against faults in the memory system. It is demonstrated that the presented backend can detect all single bit flips in memory that would be missed by an error detection scheme that operates on the LLVM intermediate representation of programs. The presented compiler backend is obtained by modifying the LLVM backend for the x86 architecture. On a subset of SPEC CINT2006 the runtime overhead incurred by the backend modifications amounts to 1.50x for the 32-bit processor architecture i386, and 1.13x for the 64-bit architecture x86_64. To achieve comprehensive detection of memory faults, the modified backend implements an adjusted calling convention that leaves library function calls transparent and intact.

Technological advances drive hardware to ever smaller feature sizes, causing devices to become more vulnerable to transient faults. Applications can be protected against faults by adding error detection and recovery measures in software. This is popularly achieved by applying automatic program transformations. However, transformations applied to program representations at abstraction levels higher than machine instructions are fundamentally incapable of protecting against vulnerabilities that are introduced during compilation. In particular, a large proportion of a program’s memory accesses are introduced by the compiler backend. This report presents a backend that protects these accesses against faults in the memory system. It is demonstrated that the presented backend can detect all single bit flips in memory that would be missed by an error detection scheme that operates on the LLVM intermediate representation of programs. The presented compiler backend is obtained by modifying the LLVM backend for the x86 architecture. On a subset of SPEC CINT2006 the runtime overhead incurred by the backend modifications amounts to 1.50x for the 32-bit processor architecture i386, and 1.13x for the 64-bit architecture x86_64. To achieve comprehensive detection of memory faults, the modified backend implements an adjusted calling convention that leaves library function calls transparent and intact.

The thesis aims to develop a method for extending the language platform Storm with a Java frontend.The project was conducted using an Action Research methodology and highlights triumphs andchallenges. Despite the significant overhead related to note generation and problem statementformulation, this methodology proved beneficial in identifying problems and providing the framework tosolve them. The first research question (RQ.1) evaluates to what extent the language platform Storm is suitable forimplementing the object oriented language Java. Using Storm, only a BNF and a specification for three-address code instructions are needed. Despite encountering difficulties during the implementation, theplatform offers tools that allow comprehensive customization of the new language's intended behaviorand functionality. The second research question (RQ.2) explores a suitable method for implementing a new language inStorm. It is suggested to first implement a foundational structure comprising of statements, blocks,scope handling and variable declarations. From this foundation, new functionalities can be graduallyintroduced and tested by connecting them to the appropriate location in the structure. When allfunctionality is added and tested a refactoring step can take place to modify the BNF if needed.

Compilers, complex programs with the potential to greatly facilitate software and hardware design. This thesis focuses on enhancing the Spade hardware description language, known for its user-friendly approach to hardware design. In the realm of hardware development data size - for numerical values data size is known as "wordlength" - plays a critical role for reducing the hardware resources. This study presents an innovative approach that seamlessly integrates wordlength inference directly into the Spade language, enabling the over-estimation of numeric data sizes solely from the program's source code. The methodology involves iterative development, incorporating various smaller implementations and evaluations, reminiscent of an agile approach. To assess the efficacy of the wordlength inference, multiple place and route operations are performed on identical Spade code using various versions of nextpnr. Surprisingly, no discernible impact on hardware resource utilization emerges from the modifications introduced in this thesis. Nonetheless, the true significance of this endeavor lies in its potential to unlock more advanced language features within the Spade compiler. It is important to note that while the wordlength inference proposed in this thesis shows promise, it necessitates further integration efforts to realize its full potential.

Computer architecture has looming challenges with finding program parallelism, process technology limits, and limited power budget. To navigate these challenges, a deeper understanding of parallel programs is required. I will discuss the task graph representation and how it enables programmers and compiler optimizations to understand and exploit dynamic aspects of the program. I will present Contech, which is a high performance framework for generating dynamic task graphs from arbitrary parallel programs. The Contech framework supports a variety of languages and parallelization libraries, and has been tested on both x86 and ARM. I will demonstrate how this framework encompasses a diversity of program analyses, particularly by modeling a dynamically reconfigurable, heterogeneous multi-core processor.

Les serveurs Internet sont des logiciels particuliers. Ils doivent répondre aux demandes d'un grand nombre de clients distants, supporter leur évolution et être robustes car ils ne s'arrêtent jamais. Les modèles de concurrence permettent d'entrelacer les traitements d'un grand nombre de clients. Aucun consensus ne se dégage sur un meilleur modèle. Pour s'abstraire du modèle de concurrence, je propose un modèle de développement de serveurs Internet. Les outils de vérification formelle permettent d'accroître la sûreté des logiciels mais il est nécessaire de leur fournir un modèle simple du logiciel. Le modèle de développement que je propose est utilisé pour générer le serveur et son modèle formel. Le décodage d'une requête cliente dépend du modèle de concurrence. Je propose d'utiliser un générateur d'analyseur syntaxique qui s'abstrait de ce problème et automatise le développement du décodage / Internet servers are software with specific features. Indeed, they answer request of wide and distant clients, support the customer evolution and be robust because they never stop. The concurrency models allow to interleave the statements of wide customers. No general agreement frees on a better model. To abstract himself from the concurrency model, I propose a development model of Internet servers. Model checkers allow to increase the software safety. But, it is necessary to provide a simple model of software to check it. I propose to use my development model of servers in order to genrate ther server automatically and its formal model. Finally as the request parsing depends on the concurrency model, I propose to use Tatoo, a parser generator. Tatoo abstracts himself from this dependency and automates the development of parsing

This research explores the Automation Interface created by Beckhoff through introducinga compiler solution. Today machine builders have to be able to build machinesor plants in different sizes and provide many variations of the machine orplant types. Automatic code generation can be used in the aspect to reuse code thathas been tested and is configurable to match the desired functionality. Additionally,the use of a pre-existing API could potentially result in less engineering resourceswasted in developing automatic code generation. This thesis aims to evaluate theAutomation Interface (AI) tool created by Beckhoff. This is accomplished throughmeans of incorporating the API functions into a compiler solution. The solution isdesigned to export the information required through an XML-file to generate PLCapplications.The generated PLC-code will be in Structured Text. In order to createa functional PLC-application, the construction of software requirements and testcases are established. The solution is then validated by means of generating a dataloggerto illustrate the usage. The exploratory research revealed both the benefitsand cons of using AI to a compiler solution. The evaluation indicated that the AutomationInterface can reduce engineering effort to produce a compiler solution, butthe learning curve of understanding the underlying components that work with theAPI required a great deal of effort.

Upgrading or migrating a build system can be a daunting task. Complete build system migration requires significant effort. To make the process more effective, we automated the first steps of migration, and attempted to analyze the new build results to find anomalies. Our findings show promise for automation as a first step of migration, and we see that automated evaluation could have some potential.

Este trabalho tem como fulcro o desenvolvimento de um gerador de analisadores sintáticos do tipo top-down para gramáticas LL(1) com entrada gráfica da gramática, bem como uma comparação do mesmo com outros geradores em uso no mercado. Como resultado foi obtido um gerador totalmente funcional, e foi mostrado como ele é superior aos outros analisadores. São descritos detalhes da implementação e foi elaborado um manual de uso do sistema implementado em Java independente de ambientes de programação. / This thesis has as its main goal the development a parser generator using top-down syntax analysis for LL(1) grammars. Its input is a graph grammar. A comparison with available parser generators is also presented. As a result a fully executable generator, and the fact that it is superior to the other generators was demonstrated. This work contains details of the implementation, and presents a users manual of the system, which was implemented in Java. The system is independent of programming environments.