O ChipCflow é o projeto de uma ferramenta para execução de algoritmos utilizando o modelo a fluxo de dados dinâmico em hardware reconfigurável. Tem como principal objetivo utilizar o modelo de arquitetura a fluxo de dados, associado ao conceito de arquiteturas reconfiguráveis, para acelerar programas de aplicação escritos em C. Essa aceleração vai acontecer nas partes mais intensas de processamento (exemplo: loops), através da execução direta em hardware, aproveitando ao máximo o paralelismo considerado natural do modelo a fluxo de dados. O módulo de conversão C em grafo a fluxo de dados, desenvolvido neste trabalho de doutoramento, é parte fundamental no desenvolvimento do projeto ChipCflow e se trata de um pré-compilador C que gera código VHDL para os operadores a fluxo de dados a partir de módulos do programa de aplicação escrito originalmente em C. É possível considerar como principal resultado dessa tese, a implementação de algoritmos a partir de uma linguagem C em grafo a fluxo de dados no modelo proposto no projeto ChipCflow, onde os operadores a fluxo de dados são os já tradicionalmente conhecidos, e até mesmo a forma de interconexão também, entretanto a forma de abordar essa implementação, em VHDL, e na forma de fluxo de dados dinâmico, torna o modelo proposto, tanto para o hardware como para o compilador, uma característica única existente até o momento. / ChipCflow is a tool for algorithms execution using a data dynamic flow in reconfigurable hardware. The main purpose of the work is to use the data flow architecture model, associated to the concept of reconfigurable architectures, to speed up C written applications. The program acceleration happens in the most intensive processing parts (example: loops), through direct hardware execution, using to advantage of the natural parallelism of the data flow model. The C conversion module in data flow graph is the basic part in the development of the ChipCflow project and the specific objective of the developed work. In this work we present detais of the C precompiler that generates VHDL code for the data flow operators modules of the written program of the original application in C. It is possible to consider as the main result of this thesis, the implementation of algorithms from a C language in the data flow graph model proposed in the project ChipCflow, where the operators to the data stream are typically already known, and even the way interconnection too, but how to approach the implementation in VHDL, and as a dynamic data flow, makes the proposed model for both the hardware and the compiler, a feature only available so far.

O ChipCflow é o projeto de uma ferramenta para execução de algoritmos utilizando o modelo a fluxo de dados dinâmico em hardware reconfigurável. Tem como principal objetivo utilizar o modelo de arquitetura a fluxo de dados, associado ao conceito de arquiteturas reconfiguráveis, para acelerar programas de aplicação escritos em C. Essa aceleração vai acontecer nas partes mais intensas de processamento (exemplo: loops), através da execução direta em hardware, aproveitando ao máximo o paralelismo considerado natural do modelo a fluxo de dados. O módulo de conversão C em grafo a fluxo de dados, desenvolvido neste trabalho de doutoramento, é parte fundamental no desenvolvimento do projeto ChipCflow e se trata de um pré-compilador C que gera código VHDL para os operadores a fluxo de dados a partir de módulos do programa de aplicação escrito originalmente em C. É possível considerar como principal resultado dessa tese, a implementação de algoritmos a partir de uma linguagem C em grafo a fluxo de dados no modelo proposto no projeto ChipCflow, onde os operadores a fluxo de dados são os já tradicionalmente conhecidos, e até mesmo a forma de interconexão também, entretanto a forma de abordar essa implementação, em VHDL, e na forma de fluxo de dados dinâmico, torna o modelo proposto, tanto para o hardware como para o compilador, uma característica única existente até o momento. / ChipCflow is a tool for algorithms execution using a data dynamic flow in reconfigurable hardware. The main purpose of the work is to use the data flow architecture model, associated to the concept of reconfigurable architectures, to speed up C written applications. The program acceleration happens in the most intensive processing parts (example: loops), through direct hardware execution, using to advantage of the natural parallelism of the data flow model. The C conversion module in data flow graph is the basic part in the development of the ChipCflow project and the specific objective of the developed work. In this work we present detais of the C precompiler that generates VHDL code for the data flow operators modules of the written program of the original application in C. It is possible to consider as the main result of this thesis, the implementation of algorithms from a C language in the data flow graph model proposed in the project ChipCflow, where the operators to the data stream are typically already known, and even the way interconnection too, but how to approach the implementation in VHDL, and as a dynamic data flow, makes the proposed model for both the hardware and the compiler, a feature only available so far.

Software as a service is an emerging but important aspect of the web. WebServices play a vital role in providing it. Web Services are commonly provided in one of two architectural styles: a "REpresentational State Transfer" (REST), or using the "Simple Object Access Protocol" (SOAP.) Originally most web content was text and small images. But more recent services involve complex data structures including text, images, audio, and video. The task of optimizing data to provide delivery of these structures is a complex one, involving both theoretical and practical aspects. In this thesis work, I have considered two architectures developed in the REST architectural style and tested them on mixes of data types (plain text, image, audio) being retrieved from a file system or database. The payload which carries the actual content of a data transmission process can either be in Extensible Markup Language (XML) or JavaScript Object Notation (JSON). Both of these language notations are widely used. The two architectures used in this thesis work are titled as Scenario 1 and Scenario 2. Scenario 1 proposes two different cases for storing, retrieving and presenting the data via a REST web service. We investigate the question of what is the best way to provide different data types (image, audio) via REST Web Service. Payload size for JSON and XML are compared. Scenario 2 proposes an enhanced and optimized architecture which is derived from the pros of the first two cases in Scenario 1. The proposed architecture is best suited for retrieving and serving non-homogeneous data as a service in a homogenous environment. This thesis is composed of theoretical and practical parts. The theory part contains the design and principles of REST architecture. The practical part has a Web Service provider and consumer model developed in Java. The practical part is developed using the Spring MVC framework and Apache CXF, which provides an implementation using JAX-RS, the Java API for RESTful services. A glossary of acronyms used in this thesis appears in the appendix on page 101.

Emerging low power, embedded, wireless sensor devices are useful for wide range of applications, yet have very limited processing storage and especially energy resources. Sensor networks have a wide variety of applications in medical monitoring, environmental sensing and military surveillance. Due to the large number of sensor nodes that may be deployed and the required long system lifetimes, replacing the battery is not an option. Sensor systems must utilize the minimal possible energy while operating over a wide range of operating scenarios. The most of the efforts in the energy management in sensor networks have concentrated on minimizing energy consumption in the communication subsystem. Some researchers have also dealt with the issue of minimizing the energy in computing subsystem of a sensor network node. Some proposals using energy aware software have also been made. Relatively little work has been done on compiler controlled energy management in sensor networks. In this thesis, we present our investigations on how compiler techniques can be used to minimize CPU energy consumption in sensor network nodes. One effectively used energy management technique in general purpose processors, is dynamic voltage scaling. In this thesis we implement and evaluate a compiler assisted DVS algorithm and show its usefulness for a small sensor node processor. We were able to achieve an energy saving of 29% with a little performance slowdown. Scratchpad memories have been widely used for improving performance. In this thesis we show that if the scratchpad size for the system is chosen carefully, then large energy savings can be achieved by using a compiler assisted scratchpad allocation policy. With a small size of 512 byte scratchpad memory we were able to achieve 50% of energy savings. We also studied the behavior of dynamic voltage scaling in presence of scratchpad memory. Our results show that in presence of scratchpad memory less opportunities are found for applying dynamic voltage scaling techniques. The sensor network community lacks a comprehensive benchmark suite, for our study we also implemented a set of applications, representative of computational workload on sensor network nodes. The techniques studied in this thesis can easily be integrated with existing energy management techniques in sensor networks, yielding in additional energy savings.

Το αντικείμενο που πραγματεύεται η παρούσα διδακτορική διατριβή σχετίζεται με την ανάπτυξη βελτιστοποιητικών τεχνικών μεταγλώττισης για επαναπροσδιοριζόμενα ολοκληρωμένα συστήματα γενικού και ειδικού σκοπού. Στόχος είναι η βελτιστοποίηση της εκτέλεσης των εφαρμογών ως προς την ταχύτητα, την επιφάνεια ολοκλήρωσης και την κατανάλωση ισχύος. Αυτό επιτυγχάνεται με την εισαγωγή πρωτότυπων τεχνικών μεταγλώττισης αλλά και από την ανεύρεση βέλτιστων αρχιτεκτονικών. Η αυτοματοποίηση των μεθοδολογιών επιτυγχάνεται με την ανάπτυξη εργαλείων βελτιστοποίησης που υλοποιούν την μεθοδολογία μεταγλώττισης. Τα πειράματα έδειξαν γρήγορο προσδιορισμό βέλτιστων λύσεων και σημαντικές βελτιώσεις στην ταχύτητα, επιφάνεια ολοκλήρωσης και κατανάλωση ισχύος για μια σειρά από εφαρμογές ψηφιακής επεξεργασίας σήματος. / The research material that is presented in this PhD Phesis is related with developement of compilation techniques for reconfigurable systems and application specific integrated circuits. The objective is the optimization of the execution of the applications in terms of speed area and power consumption in these architectures. This is achieved by developing original compiling techniques and efficient architecture instances. Moreover, one of the fundamental objectives of this thesis is the automation of these techniques for fast solution determination. Experiments showed that applications are executed faster while keeping the area and power overhead low. The experiments are based on a set of Digital Signal Processing applications.

Το αντικείμενο της παρούσας διδακτορικής διατριβής εστιάζεται στην ανάπτυξη αποδοτικών τεχνικών μεταγλώττισης για επαναπροσδιοριζόμενα ολοκληρωμένα συστήματα αρχιτεκτονικών πίνακα. Χρησιμοποιήθηκαν εφαρμογές που κυριαρχούνται από δεδομένα για τον έλεγχο των μεθοδολογιών. Σκοπός είναι να βελτιστοποιηθεί η εκτέλεση των εφαρμογών ως προς χαρακτηριστικά των επαναπροσδιοριζόμενων συστημάτων όπως η απόδοση, ο αριθμός εντολών ανά κύκλο ρολογιού, η επιφάνεια ολοκλήρωσης και ο βαθμός χρησιμοποίησης των επεξεργαστικών πόρων. Αυτό επιτυγχάνεται με την εισαγωγή πρωτότυπων τεχνικών χαρτογράφησης αλλά και την εύρεση βέλτιστων αρχιτεκτονικών. Στο πρώτο τμήμα της διατριβής υλοποιήθηκε η έρευνα, ανάπτυξη και αυτοματοποίηση τεχνικών μεταγλώττισης για επαναπροσδιοριζόμενα συστήματα αρχιτεκτονικών πίνακα. Κύριο χαρακτηριστικό αυτών των αρχιτεκτονικών είναι ύπαρξη μεγάλου αριθμού επεξεργαστικών στοιχείων που δουλεύουν παράλληλα με αποτέλεσμα να επιταχύνουν την εκτέλεση εφαρμογών που εμφανίζουν παραλληλία πράξεων. Η λειτουργία τους σε ενσωματωμένα συστήματα είναι αυτή ενός συνεπεξεργαστή. Η έρευνα πάνω σε επαναπροσδιοριζόμενες αρχιτεκτονικές πίνακα έχει αποκτήσει μεγάλο ενδιαφέρον λόγω της ευελιξίας, της επεκτασιμότητας και της απόδοσής τους, ιδιαίτερα σε εφαρμογές που κυριαρχούνται από δεδομένα. Η μεταγλώττιση, όμως, εφαρμογών πάνω σε αυτές χαρακτηρίζεται από υψηλή πολυπλοκότητα. Απαιτούνται κατάλληλα εργαλεία και ειδικές μεθοδολογίες χαρτογράφησης για την εκμετάλλευση των χαρακτηριστικών αυτών των αρχιτεκτονικών. Με αυτό το σκεπτικό, προτάθηκε μια πρωτότυπη επαναστοχεύσιμη μεθοδολογία χαρτογράφησης εφαρμογών, η οποία επιπλέον έχει αυτοματοποιηθεί με τη χρήση ενός πρότυπου εργαλείου μεταγλώττισης που στοχεύει σε ένα αρχιτεκτονικό παραμετρικό πρότυπο. Αποτέλεσμα ήταν η εύρεση των βέλτιστων αρχιτεκτονικών με βάσει την απόδοση, τον αριθμό των εντολών ανά κύκλο ρολογιού και το χρόνο εκτέλεσης του εργαλείου, για μια ομάδα εφαρμογών. Η αποδοτικότητα μιας επαναπροσδιοριζόμενης αρχιτεκτονικής πίνακα ως προς την ταχύτητα και το κόστος σε υλικό είναι δύσκολο να μετρηθεί, για αυτό έχουν υπάρξει λίγες έρευνες που μελετούν την επίδραση αρχιτεκτονικών παραμέτρων πάνω σε παράγοντες όπως η επιφάνεια ολοκλήρωσης και ο αριθμός εντολών ανά κύκλο ρολογιού. Επιπλέον, καμιά εργασία δεν έχει εξετάσει την επίδραση πολλαπλασιαστών ενσωματωμένων στα επεξεργαστικά στοιχεία των επαναπροσδιοριζόμενων αρχιτεκτονικών. Χρησιμοποιώντας την υπάρχουσα επαναστοχεύσιμη μεθοδολογία μεταγλώττισης και μια παραμετρική υλοποίηση της αρχιτεκτονικής σε γλώσσα περιγραφής υλικού, εξετάζουμε την επίδραση των πολλαπλασιαστών από τη μεριά της χαρτογράφησης και της αρχιτεκτονικής. Επίσης, περιγράφεται η πρωτότυπη μεθοδολογία χαρτογράφησης που εισήχθη με σκοπό την αποδοτική λειτουργία του αλγορίθμου Fast Fourier Transform (FFT) πάνω σε επαναπροσδιοριζόμενα συστήματα αρχιτεκτονικών πίνακα. Ο αλγόριθμος FFT χαρακτηρίζεται από μεγάλο αριθμό πράξεων κυρίως πολλαπλασιασμών που επιβραδύνουν την απόδοση μιας επαναπροσδιοριζόμενης αρχιτεκτονικής. Εκμεταλλευόμενοι την ύπαρξη εσωτερικής επαναληπτικής δομής μέσα στον αλγόριθμο και χρησιμοποιώντας μια επαναπροσδιοριζόμενη αρχιτεκτονική 16 επεξεργαστικών στοιχείων, αναπτύξαμε μια πρωτότυπη τεχνική χαρτογράφησης. Επιπρόσθετα, η τεχνική μας λαμβάνει υπόψη την ιεραρχία μνήμης μεταξύ κύριας μνήμης και επαναπροσδιοριζόμενης αρχιτεκτονικής για την περαιτέρω επιτάχυνση εκτέλεσης του αλγορίθμου FFT. Η χρήση της προτεινόμενης τεχνικής χαρτογράφησης οδηγεί σε επίτευξη βαθμού χρησιμοποίησης των επεξεργαστικών στοιχείων άνω του 90%, τιμή που είναι τουλάχιστον 37% υψηλότερη από την καλύτερη τιμή της βιβλιογραφίας. / The object of this PhD thesis focuses on developing efficient mapping techniques for coarse grain reconfigurable build arrays. Data intensive applications were used to evaluate the proposed methodologies. The aim is to optimize the applications’ performance on characteristics targeting reconfigurable characteristics such as performance, instructions per cycle, area of integration and processing resource utilization. This is achieved by introducing novel mapping techniques and finding optimal architectures. In the first part of the thesis research, development and automation of mapping techniques was carried out targeting coarse grain reconfigurable arrays. The main feature of these architectures is the presence of a large number of processing elements working in parallel thus speeding up the execution of applications featuring parallel operations. The function of these processing elements in embedded systems resembles that of a coprocessor. The research on reconfigurable array architectures has gained considerable interest because of their flexibility, scalability and performance, particularly in data intensive applications. Nevertheless, compiling these applications on reconfigurable architectures is characterized by high degree of complexity. Appropriate tools and special mapping methodologies are needed to exploit the characteristics of these architectures. Bearing this in mind, we proposed a novel reconfigurable methodology for mapping applications, which has also been automated with the use of a prototype compiler tool aiming at a parametric architectural model. The result was finding the best architectures on the basis of performance, the instructions per cycle term and the tool execution time for a sample set of applications. It is difficult to evaluate the efficiency of a reconfigurable array architecture table in terms of speed and area of integration, so there have been few cases studying the effect of architectural parameters on factors such as surface integration and the number of instructions per clock cycle. Moreover, no work has examined the multipliers’ impact embedded in reconfigurable architectures processing elements. Using the existing reconfigurable mapping methodology and a parametric implementation of the architecture in hardware description language, we examine the effect of multipliers on the part of the mapping phase and architecture. We also describe an original mapping methodology introduced for the purpose of efficiently mapping the Fast Fourier Transform (FFT) algorithm on reconfigurable array architectures. The FFT algorithm is characterized by a large number of operations primarily multiplications that slow the performance of a reconfigurable architecture. Exploiting the existence of an internal structure inside the FFT algorithm and by the use of a reconfigurable architecture template of 16 processing elements, we developed a novel mapping technique. Additionally, our technique takes into account the memory hierarchy between main memory and reconfigurable architecture in order to further accelerate the implementation of the FFT algorithm. Using the proposed mapping technique results in processing elements utilization of over 90% value which is at least 37% better than the best value of the related literature.

Notre étude de la compilation sous-polyédrique est dominée par l’introduction de la notion l’ordonnancement affine sous-polyédrique, pour laquelle nous proposons une technique utilisant des sous-polyèdres (U)TVPI. Dans ce cadre, nous introduisons des algorithmes capables de construire des sous-approximations de systèmes de contraintes résultant de problèmes d’ordonnancement affine. Cette technique repose sur des algorithmes polynomiaux simples pour approcher un polyèdre quelconque par un polyèdre (U)TVPI. Nos algorithmes sont suffisamment génériques pour s’appliquer à de nombreux problèmes d’ordonnancement, de parallélisation, et d’optimisation de boucles, réduisant leur complexité temporelle à des fonctions polynomiales. Nous introduisons également une méthode pour la génération de code utilisant des algorithmes sous-polyédriques, tirant parti de la faible complexité des sous-polyèdres (U)TVPI. Dans ce cadre, nous montrons comment réduire la complexité associée aux générateurs de code les plus populaires, ramenant la complexité de plusieurs facteurs exponentiels à des fonctions polynomiales. Nombre de ces techniques sont évaluées expérimentalement. Pour cela, nous avons réalisé une version modifiée du compilateur PLuTo, capable de paralléliser et d’optimiser des nids de boucles pour des architectures multi-cœurs à l’aide de transformations affines, et notamment de partitionnement (tiling). Nous montrons qu’une majorité des noyaux de calcul de la suite Polybench (2.0) peut être manipulée à l’aide de notre technique d’ordonnancement, en préservant la faisabilité des polyèdres lors des sous-approximations. L’utilisation des systèmes approchés par des sous-polyèdres conduit à des gains asymptotiques en complexité, qui se traduit par des réductions significatives en temps de compilation, par rapport à un solveur de programmation linéaire de référence. Nous vérifions également que le code généré par notre prototype de parallélisation sous-polyédrique est compétitif par rapport à la performance du code généré par Pluto. / The goal of this thesis is to design algorithms that run with better complexity when compiling or parallelizing loop programs. The framework within which our algorithms operate is the polyhedral model of compilation which has been successful in the design and implementation of complex loop nest optimizers and parallelizing compilers. The algorithmic complexity and scalability limitations of the above framework remain one important weakness. We address it by introducing sub-polyhedral compilation by using (Unit-)Two-Variable-Per-Inequality or (U)TVPI Polyhedra, namely polyhedrawith restricted constraints of the type ax_{i}+bx_{j}\le c (\pm x_{i}\pm x_{j}\le c). A major focus of our sub-polyhedral compilation is the introduction of sub-polyhedral scheduling, where we propose a technique for scheduling using (U)TVPI polyhedra. As part of this, we introduce algorithms that can be used to construct under-aproximations of the systems of constraints resulting from affine scheduling problems. This technique relies on simple polynomial time algorithms to under approximate a general polyhedron into (U)TVPI polyhedra. The above under-approximation algorithms are generic enough that they can be used for many kinds of loop parallelization scheduling problems, reducing each of their complexities to asymptotically polynomial time. We also introduce sub-polyhedral code-generation where we propose algorithms to use the improved complexities of (U)TVPI sub-polyhedra in polyhedral code generation. In this problem, we show that the exponentialities associated with the widely used polyhedral code generators could be reduced to polynomial time using the improved complexities of (U)TVPI sub-polyhedra. The above presented sub-polyhedral scheduling techniques are evaluated in an experimental framework. For this, we modify the state-of-the-art PLuTo compiler which can parallelize for multi-core architectures using permutation and tiling transformations. We show that using our scheduling technique, the above under-approximations yield polyhedra that are non-empty for 10 out of 16 benchmarks from the Polybench (2.0) kernels. Solving the under-approximated system leads to asymptotic gains in complexity, and shows practically significant improvements when compared to a traditional LP solver. We also verify that code generated by our sub-polyhedral parallelization prototype matches the performance of PLuTo-optimized code when the under-approximation preserves feasibility.

Submitted by Milena Rubi (milenarubi@ufscar.br) on 2016-10-18T13:50:17Z No. of bitstreams: 1 FERREIRA_Maria_2015.pdf: 44702801 bytes, checksum: d58773cbbac5f088372d16f186805b06 (MD5) / Approved for entry into archive by Milena Rubi (milenarubi@ufscar.br) on 2016-10-18T13:50:31Z (GMT) No. of bitstreams: 1 FERREIRA_Maria_2015.pdf: 44702801 bytes, checksum: d58773cbbac5f088372d16f186805b06 (MD5) / Approved for entry into archive by Milena Rubi (milenarubi@ufscar.br) on 2016-10-18T13:50:43Z (GMT) No. of bitstreams: 1 FERREIRA_Maria_2015.pdf: 44702801 bytes, checksum: d58773cbbac5f088372d16f186805b06 (MD5) / Made available in DSpace on 2016-10-18T13:51:11Z (GMT). No. of bitstreams: 1 FERREIRA_Maria_2015.pdf: 44702801 bytes, checksum: d58773cbbac5f088372d16f186805b06 (MD5) Previous issue date: 2015-12-18 / Coordenação de Aperfeiçoamento de Pessoal de Nível Superior (CAPES) / Compiler error messages should allow programmers to understand and solve quickly problems found during the compilation process. However, compilers usually issue short contextless messages with little information and with terms that are difficult to understand. This work introduces the plug-in Error Message System (EMS) that allows the presentation of easy-to-understand and more meaningful error messages. EMS is a plug-in to the Eclipse IDE. It is highly configurable through Domain Specific Languages (DSLs). The DSLs allow that regular users build their own error messages and share them. Beginner programmers can use a set of error messages adapted to them thus reducing the time of understanding and correction of compilation errors. / As mensagens de erro dos compiladores devem permitir que os programadores compreendam e solucionem os problemas encontrados durante o processo de compilação rapidamente. Entretanto, os compiladores usualmente emitem mensagens curtas, sem contexto, pouco informativas e com termos de difícil compreensão. Este trabalho apresenta o plug-in Error Message System (EMS) que permite a apresentação das mensagens de erro mais fáceis de entender e mais informativas. EMS é um plugin para a IDE Eclipe e é altamente configurável através de linguagens específicas de domínio(LED). As LEDs permitem que usuários comuns façam suas próprias mensagens de erro e as compartilhem. Programadores iniciantes podem utilizar um conjunto de mensagens adaptadas a eles, reduzindo o tempo de compreensão e correção dos erros de compilação.

Atuais paradigmas correntes de programação de software, mais precisamente o Paradigma Imperativo (PI) e o Paradigma Declarativo (PD), apresentam deficiências que afetam o desempenho das aplicações e a obtenção de “desacoplamento” (ou acoplamento mínimo) entre elementos de software. Com o objetivo de amenizar essas deficiências, foi desenvolvido o Paradigma Orientado a Notificações (PON). O PON se inspira nos conceitos do PI (e.g. objetos) e do PD (e.g. base de fatos e regras), mas altera a essência da execução ou inferência lógica-causal. Basicamente, o PON usa objetos para tratar de fatos e regras na forma de composições de outros objetos menores que, entretanto, apresentam características comportamentais de certa autonomia, independência, reatividade e colaboração por meio de notificações pontuais para fins de inferência. Isto dito, salienta-se que a materialização dos conceitos do PON se deu por meio de um arquétipo ou Framework elaborado em linguagem de programação C++. Tal materialização do PON vem sendo utilizada como uma alternativa para o desenvolvimento de aplicações sob o domínio desse paradigma e possibilitou, de fato, a criação de aplicações para ambientes computacionais usuais baseados na chamada arquitetura Von Neumann. Apesar destas contribuições para com a sua materialização, o desenvolvimento de aplicações no PON ainda não apresentava resultados satisfatórios em termos de desempenho tal qual deveria a luz do seu cálculo assintótico, nem a facilidade de programação que seria uma das suas características principais. Nesse âmbito, o presente trabalho propõe como evolução para o estado da técnica do PON a criação de uma linguagem e compilador para o paradigma. Sendo assim, este trabalho apresenta a definição da linguagem criada com a utilização de exemplos práticos guiados pelo desenvolvimento de aplicações. Subsequentemente são apresentados detalhes do compilador bem como sua estrutura. Para demonstrar a evolução do estado da técnica do paradigma, no tocante a desempenho (e.g. tempo de processamento) e facilidade de programação foram realizados estudos comparativos com a utilização da linguagem e compilador. Os estudos comparativos foram guiados com a elaboração de dois softwares denominados aplicação Mira ao Alvo e aplicação de Vendas. Essas aplicações foram desenvolvidas com base na linguagem PON e foram realizados experimentos simulando sequências de execução com o intuito de avaliar o tempo de processamento para o resultado gerado pelo compilador PON. Ainda, tais experimentos possibilitaram a avaliação de maneira subjetiva da linguagem de programação PON no tocante a facilidade de programação. Deste modo, foi possível observar com tais estudos comparativos que os resultados apresentados pelo compilador PON foram satisfatórios quando comparados aos resultados obtidos pelo Framework e por aplicações equivalentes desenvolvidas baseadas no Paradigma Orientado a Objetos (POO). / The current software development paradigms, specifically the Imperative Paradigm (IP) and the Declarative Paradigm (DP), have weaknesses that affect the applications performance and decoupling (or minimal coupling) between the software modules. In order to provide a solution regarding these weaknesses, the Notification Oriented Paradigm (NOP) was developed. NOP is inspired by the concepts of the IP (e.g. objects) and DP (e.g. base of facts and Rules). Basically, NOP uses objects to deal with facts and Rules as compositions of other, smaller, objects. These objects have the following behavioral characteristics: autonomy, independence, responsiveness and collaboration through notifications. Thus, it’s highlighted that the realization of these concepts was firstly instantiated through a Framework developed in C++. Such NOP materialization has been used as an alternative for Application development in the domain of this paradigm and made possible, in fact, the creation of applications for typical computing environments based on Von Neumann architecture. The development of the C++ materialization of NOP has not presented satisfactory results in terms of performance as it should when taking into account its asymptotic calculation and programming facility. In this context, this work presents an evolution of NOP by creating a specific programming language, and its respective compiler, for this paradigm. Therefore, this work presents the language definition and the details of the development of its compiler. To evaluate the evolution regarding to performance (e.g. processing time) and programming facility, some comparative studies using the NOP language and compiler are presented. These comparative studies were performed by developing two software applications called Target and Sales Application. These applications have been developed based on NOP language, and the experiments were performed simulating sequences of execution in order to evaluate the processing time for the generated results by NOP compiler. Still, these experiments allowed the evaluation of NOP programming language, in a subjective way, regarding to ease programming. Thus, with such comparative studies, it was possible to observe that the results presented by the compiler NOP were satisfactory when compared to the results achieved via Framework and for equivalent applications developed based on the Oriented Object Paradigm (OOP).

Atuais paradigmas correntes de programação de software, mais precisamente o Paradigma Imperativo (PI) e o Paradigma Declarativo (PD), apresentam deficiências que afetam o desempenho das aplicações e a obtenção de “desacoplamento” (ou acoplamento mínimo) entre elementos de software. Com o objetivo de amenizar essas deficiências, foi desenvolvido o Paradigma Orientado a Notificações (PON). O PON se inspira nos conceitos do PI (e.g. objetos) e do PD (e.g. base de fatos e regras), mas altera a essência da execução ou inferência lógica-causal. Basicamente, o PON usa objetos para tratar de fatos e regras na forma de composições de outros objetos menores que, entretanto, apresentam características comportamentais de certa autonomia, independência, reatividade e colaboração por meio de notificações pontuais para fins de inferência. Isto dito, salienta-se que a materialização dos conceitos do PON se deu por meio de um arquétipo ou Framework elaborado em linguagem de programação C++. Tal materialização do PON vem sendo utilizada como uma alternativa para o desenvolvimento de aplicações sob o domínio desse paradigma e possibilitou, de fato, a criação de aplicações para ambientes computacionais usuais baseados na chamada arquitetura Von Neumann. Apesar destas contribuições para com a sua materialização, o desenvolvimento de aplicações no PON ainda não apresentava resultados satisfatórios em termos de desempenho tal qual deveria a luz do seu cálculo assintótico, nem a facilidade de programação que seria uma das suas características principais. Nesse âmbito, o presente trabalho propõe como evolução para o estado da técnica do PON a criação de uma linguagem e compilador para o paradigma. Sendo assim, este trabalho apresenta a definição da linguagem criada com a utilização de exemplos práticos guiados pelo desenvolvimento de aplicações. Subsequentemente são apresentados detalhes do compilador bem como sua estrutura. Para demonstrar a evolução do estado da técnica do paradigma, no tocante a desempenho (e.g. tempo de processamento) e facilidade de programação foram realizados estudos comparativos com a utilização da linguagem e compilador. Os estudos comparativos foram guiados com a elaboração de dois softwares denominados aplicação Mira ao Alvo e aplicação de Vendas. Essas aplicações foram desenvolvidas com base na linguagem PON e foram realizados experimentos simulando sequências de execução com o intuito de avaliar o tempo de processamento para o resultado gerado pelo compilador PON. Ainda, tais experimentos possibilitaram a avaliação de maneira subjetiva da linguagem de programação PON no tocante a facilidade de programação. Deste modo, foi possível observar com tais estudos comparativos que os resultados apresentados pelo compilador PON foram satisfatórios quando comparados aos resultados obtidos pelo Framework e por aplicações equivalentes desenvolvidas baseadas no Paradigma Orientado a Objetos (POO). / The current software development paradigms, specifically the Imperative Paradigm (IP) and the Declarative Paradigm (DP), have weaknesses that affect the applications performance and decoupling (or minimal coupling) between the software modules. In order to provide a solution regarding these weaknesses, the Notification Oriented Paradigm (NOP) was developed. NOP is inspired by the concepts of the IP (e.g. objects) and DP (e.g. base of facts and Rules). Basically, NOP uses objects to deal with facts and Rules as compositions of other, smaller, objects. These objects have the following behavioral characteristics: autonomy, independence, responsiveness and collaboration through notifications. Thus, it’s highlighted that the realization of these concepts was firstly instantiated through a Framework developed in C++. Such NOP materialization has been used as an alternative for Application development in the domain of this paradigm and made possible, in fact, the creation of applications for typical computing environments based on Von Neumann architecture. The development of the C++ materialization of NOP has not presented satisfactory results in terms of performance as it should when taking into account its asymptotic calculation and programming facility. In this context, this work presents an evolution of NOP by creating a specific programming language, and its respective compiler, for this paradigm. Therefore, this work presents the language definition and the details of the development of its compiler. To evaluate the evolution regarding to performance (e.g. processing time) and programming facility, some comparative studies using the NOP language and compiler are presented. These comparative studies were performed by developing two software applications called Target and Sales Application. These applications have been developed based on NOP language, and the experiments were performed simulating sequences of execution in order to evaluate the processing time for the generated results by NOP compiler. Still, these experiments allowed the evaluation of NOP programming language, in a subjective way, regarding to ease programming. Thus, with such comparative studies, it was possible to observe that the results presented by the compiler NOP were satisfactory when compared to the results achieved via Framework and for equivalent applications developed based on the Oriented Object Paradigm (OOP).