Thesis (Ph. D.)--University of Texas at Austin, 2002. / Vita. Includes bibliographical references. Available also from UMI Company.

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The experience gained when participating in the projects of “OpenOffice.org”, “Mozilla”, “AbiWord” and other software localization has revealed that even the software developed for international markets is often insufficiently internationalized. Because of that its localization is more difficult and followed by various problems. By investigating the origin of a low software internationalization level and looking for the solution of this problem, some hypotheses have been made and tested. Tasks of the work: 1. To analyse scientific and methodical literature, related with software internationalization and discuss the theoretical aspects. 2. To analyse and compare the most frequently used compilers in terms of internationalization. 3. Experimentally internationalize the chosen compiler. After corroboration of the hypotheses, additional objectives have been made: 4. To analyze aspects of internationalization of compilers and systemize them. 5. To prepare the method of internationalization of compilers. / PĮ internacionalizavimas yra gamintojo prerogatyva ir tai yra PĮ gamybos proceso dalis. Todėl didelę įtaką jam turi gamybai naudojamų priemonių internacionalizacijos lygis. Jei priemonės nėra pakankamai internacionalizuotos, tuomet šis procesas yra neįmanomas arba reikalauja didesnių papildomų investicijų. Pavyzdžiui, akivaizdu, kad programuotojas susidurs su sunkumais kurdamas internacionalizuotą PĮ, jei programavimo priemonės neleidžia pirminiame tekste naudoti daugiakalbio teksto. Ankstesni PĮ lokalizavimo darbai [DL03] [La03] [DL04] ir Free Pascal kompiliatoriaus pritaikymo Lietuvos mokykloms [DL01] [La01] srityse atskleidė, kad lokalizuojant PĮ vis dar išskyla daugybė problemų, kurių priežastimi yra nepakankamas jos internacionalizacijos lygis. Daugelis autorių linkę šių priežasčių ieškoti PĮ gamybos (internacionalizavimo) procese [Yo01] [Ye03] [Su01]. Tačiau pagrindinės priežastys kyla iš giliau t. y. iš nepakankamo PĮ gamybos priemonių internacionalizacijos lygio. Darbe pateiktas kompiliatorių internacionalizuotumo lygio įvertinimo metodas leis įvertinti kompiliatorių internacionalizuotumo lygį. Tai leis įvertinti kompiliatorių galimybes kurti internacionalizuotą PĮ, juos palyginti internacionalizuotumo aspektu.

No description available.

Functional verification is a critical part in the hardware design process cycle, and it contributes for nearly two-thirds of the overall development time. With increasing complexity of hardware designs and shrinking time-to-market constraints, the time and resources spent on functional verification has increased considerably. To mitigate the increasing cost of functional verification, research and academia have been engaged in proposing techniques for improving the simulation of hardware designs, which is a key technique used in the functional verification process. However, the proposed techniques for accelerating the simulation of hardware designs do not leverage the performance benefits offered by multiprocessors/multi-core and heterogeneous processors available today. With the growing ubiquity of powerful heterogeneous computing systems, which integrate multi-processor/multi-core systems with heterogeneous processors such as GPUs, it is important to utilize these computing systems to address the functional verification bottleneck. In this thesis, I propose a technique for accelerating SystemC simulations across multi-core CPUs and GPUs. In particular, I focus on accelerating simulation of SystemC models that are described at both the Register-Transfer Level (RTL) and Transaction Level (TL) abstractions. The main contributions of this thesis are: 1.) a methodology for accelerating the simulation of mixed abstraction SystemC models defined at the RTL and TL abstractions on multi-core CPUs and GPUs and 2.) An open-source static framework for parsing, analyzing, and performing source-to-source translation of identified portions of a SystemC model for execution on multi-core CPUs and GPUs.

Several important compiler optimizations such as instruction scheduling and register allocation are fundamentally hard and are usually solved using heuristics or approximate solutions. In contrast, this thesis examines optimal solutions to three combinatorial problems in compiler optimization. The first problem addresses instruction scheduling for clustered architectures, popular in embedded systems. Given a set of instructions the optimal solution gives the best possible schedule for a given clustered architectural model. The problem is solved using a decomposition technique applied to constraint programming which determines the spatial and temporal schedule using an integrated approach. The experiments show that our solver can tradeoff some compile time efficiency to solve most instances in standard benchmarks giving significant performance improvements. The second problem addresses instruction selection in the compiler code generation phase. Given the intermediate representation of code the optimal solution determines the sequence of equivalent machine instructions as it optimizes for code size. This thesis shows that a large number of benchmark instances can be solved optimally using constraint programming techniques. The third problem addressed is the placement of data in memory for efficient cache utilization. Using the data access patterns of a given program, our algorithm determines a placement to reorganize data in memory which would result in fewer cache misses. By focusing on graph theoretic placement techniques it is shown that there exist, in special cases, efficient and optimal algorithms for data placement that significantly improve cache utilization. We also propose heuristic solutions for solving larger instances for which provably optimal solutions cannot be determined using polynomial time algorithms. We demonstrate that cache hit rates can be significantly improved by using profiling techniques over a wide range of benchmarks and cache configurations.

Thesis (M.S.)--Rochester Institute of Technology, 1988. / Includes bibliographical references (leaves 55-57).

Thesis (Ph.D)---University of Adelaide, Faculty of Engineering, 1995. / Includes bibliographical references.

Thesis (M.S.)--University of Texas at El Paso, 2009. / Title from title screen. Vita. CD-ROM. Includes bibliographical references. Also available online.