In this thesis, a new algorithm is proposed for the recognition of triangular, circular and rectangular traffic signs and it is implemented on an FPGA platform. The system can recognize 32 different traffic signs with high recognition accuracy. In the proposed method, first the image is segmented into red and blue regions, and according to the area of the each segment, the dominant color is decided. Then, Laplacian of Gaussian (LoG) based edge detection is applied to the segmented image which is followed by Hough Transform for shape extraction. Then, recognition based on Informative Pixel Percentage (IPP) matching is executed on the extracted shapes. The Traffic Sign Recognition (TSR) system is implemented on Virtex 5 FX70T FPGA, which has an embedded PPC440 processor. Some modules of TSR algorithm are designed in the FPGA logic while remaining modules are designed in the PPC440 processor. Work division between FPGA and PPC440 is carried out considering their capabilities and shortcomings of FPGA and processor. Benefits of using an FPGA with an embedded processor are exploited to optimize the system.

This study proposes a new method for obstacle detection and avoidance using low-level MPEG-7 visual descriptors. The method includes training a neural network with a subset of MPEG-7 visual descriptors extracted from outdoor scenes. The trained neural network is then used to estimate the obstacle presence in real outdoor videos and to perform obstacle avoidance. In our proposed method, obstacle avoidance solely depends on the estimated obstacle presence data. In this study, backpropagation algorithm on multi-layer perceptron neural network is utilized as a feature learning method. MPEG-7 visual descriptors are used to describe basic features of the given scene image and by further processing these features, input data for the neural network is obtained. The learning/training phase is carried out on specially constructed synthetic video sequence with known obstacles. Validation and tests of the algorithms are performed on actual outdoor videos. Tests on indoor videos are also performed to evaluate the performance of the proposed algorithms in indoor scenes. Throughout the study, OdBot 2 robot platform, which has been developed by the author, is used as reference platform. For final testing of the obstacle detection and avoidance algorithms, simulation environment is used. From the simulation results and tests performed on video sequences, it can be concluded that the proposed obstacle detection and avoidance methods are robust against visual changes in the environment that are common to most of the outdoor videos. Findings concerning the used methods are presented and discussed as an outcome of this study.

Thesis (M.Eng.)--Memorial University of Newfoundland, 1999. / Bibliography: leaves 100-102.

Thesis (MScEng)--Stellenbosch University, 2005. / ENGLISH ABSTRACT: This thesis investigates the possible use of NAND flash memory for a mass memory unit on a micro-satellite. The investigation begins with an analysis of NAND flash memory devices including the complexity of the internal circuitry and the occurrence of bad memory sections (bad blocks). Design specifications are produced and various design architectures are discussed and evaluated. Subsequently, a four bus serial access architecture using 16- bit NAND flash devices was chosen to be developed further. A VHDL design was created in order to realise the intended system functionality. The main functions of the design include a sustained write data rate of 24 MB/s, bad block management, multiple image storing, error checking and correction, defective device handling and reading while writing. The design was simulated extensively using NAND flash simulation models. Finally, a demonstration test board was designed and produced. This board includes an FPGA and an array of 16 8-bit NAND flash devices. The board was tested sucessfully and a write data rate of 12 MB/s was achieved along with all the other main functions. / AFRIKAANSE OPSOMMING: Hierdie tesis ondersoek die moontlike gebruik van NAND flash tegnologie as die geheue eenheid van ’n mikrosatelliet. As ’n beginpunt word NAND flash tegnologie ondersoek in terme van die kompleksiteit van interne stroombane en die voorkoms van defektiewe geheuesegmente. Daarna word ontwerpspesifikasies voortgebring en verskillende ontwerpsmoontlikhede met mekaar vergelyk. Vanuit hierdie oorwegings is daar besluit om die oplossing te implementeer met ’n vier-bus seri¨ele struktuur bestaande uit 16-bis NAND flash toestelle. Om die ontwerpspesifikasies te realiseer, is ’n VHDL stelsel geskep. Die belangrikste funksies van hierdie stelsel is ’n konstante skryftempo van 24 MB/s, die bestuur van defektiewe geheuesegmente, die stoor van meer as een beeld, foutopsporing en -herstel, optimale werking in die geval van defektiewe geheuetoestelle en laastens, die gelyktydige lees en skryf van data. Die stelsel is breedvoerig getoets met NAND flash simulasiemodelle. Ten slotte is ’n fisiese demonstrasiebord, bestaande uit ’n FPGA en 16 8-bis NAND flash toestelle, ontwerp en gebou. Fisiese metings was ’n sukses. ’n Skryftempo van 12 MB/s is gehaal, tesame met die korrekte werking van die ander hooffunksies.

Orientador: Rodolfo Jardim de Azevedo / Dissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação / Made available in DSpace on 2018-08-10T11:21:32Z (GMT). No. of bitstreams: 1 Sigrist_ThiagoMassariolli_M.pdf: 1159366 bytes, checksum: 1b73082be801a7391d4d5176c6e49207 (MD5) Previous issue date: 2007 / Resumo: O surgimento dos SoCs (Systems-on-Chip) levou ao desenvolvimento das metodologias de projeto baseadas em TLM (Transaction-Level Modelling), que oferecem diversas etapas de modelagem intermediárias entre a especificação pura e a descrição sintetizável RTL (Register Transfer Level ), tornando mais tratável o projeto de sistemas dessa complexidade. Levando-se em consideração que esses sistemas geralmente possuem microprocessadores como módulos principais, torna-se desejável o uso de linguagens de descrição de arquiteturas (ADLs ? Architecture Description Languages) como ArchC e suas ferramentas para que seja possível modelar esses processadores e gerar módulos simuladores para eles em uma fração do tempo tradicionalmente gasto com essa tarefa. Porém, ArchC, em sua penúltima versão, a 1.6, possui utilidade limitada para esse fim, pois os simuladores que é capaz de gerar são autocontidos, não sendo facilmente integráveis aos modelos TLM em nível de sistema como um todo. Este trabalho consiste em uma remodelagem da linguagem ArchC e sua ferramenta acsim de modo a acrescentar essa capacidade de integração aos simuladores funcionais interpretados que é capaz de gerar, dando assim origem à versão 2.0 de ArchC / Abstract: The advent of SoCs (Systems-on-Chip) lead to the development of project methodologies based on TLM (Transaction-Level Modelling), which consist of several modelling layers between pure specifications and synthesizable RTL (Register Transfer Level ) descriptions, making the complexity of such systems more manageable. Considering that those systems usually have microprocessors as main modules, it is desirable to use architecture description languages (ADLs) like ArchC and its toolkit to model those processors and generate simulator modules for them in a fraction of the time usually spent in that task. However, ArchC, in its previous version, 1.6, has limitations for that use, since the simulators it generates are self-contained, thus hard to integrate to TLM system-level models. This work consists in remodelling ArchC and its acsim tool, adding this ability of integration to its functional interpreted simulators, leading to version 2.0 of ArchC / Mestrado / Sistemas de Computação / Mestre em Ciência da Computação

As the speed of operation of VLSI devices has increased, delay fault testing has become a more important factor in VLSI testing. Due to the large number of gates in a VLSI circuit, the gate level test generation methodologies may become infeasible for delay test generation. In this work, a new behavioral delay fault model that aims at simplifying the delay test generation problem for digital circuits is presented. The model is defined using VHDL. It is shown that each defined behavioral level delay fault can be mapped to a gate level equivalent fault and/or physical failure. A systematic way of representing a behavioral model in terms of a data flow graph is presented. A behavioral level input-output path is defined and a strategy to generate tests for delay faults along a behavioral path is presented. It is then shown that tests developed from the behavioral model can test a gate level equivalent circuit for path delay faults. / Master of Science

In this thesis, several techniques for the test generation of VHDL behavioral models are proposed. An algorithm called HBTG, Hierarchical Behavioral Test Generator, is developed and implemented to systematically generate tests for VHDL behavioral models. HBTG accepts the Process Model Graph and the precomputed tests for the individual processes of the model from which it constructs a test sequence that exercises the model hierarchically. The construction of the test sequence is automatic if the tests for the individual processes of the model are provided. The test sequence derived can be used for the simulation of the model. By comparing the simulation outputs with the data sheet or the design specifications of the corresponding circuit, a user can tell if the functionality of the model is as expected or any functional faults exist. Simulation results and conclusions are given. Some suggestions for further improvements of the program are discussed. / Master of Science

This thesis describes the development of BACKANN, a tool for the back annotation of timing delays into VHDL models. BACKANN uses the Process Model Graph and the VHDL behavioral model generated by the Modeler's Assistant as the base for backannotation. BACKANN determines the delay values that are required for the signal assignments in the behavioral model. It generates a gate-level design of the model using the Synopsys Design Compiler. It extracts the values for the delays required from the gate-level design. It then back-annotates these values into the VHDL behavioral model. BACKANN is thus a design automation tool that helps the development of VHDL behavioral models with realistic timing and thus quickens the design cycle. / Master of Science

This thesis describes the development of the Process Test Generation (PTG) software for the testing of single-process VHDL behavioral models. The PTG software, along with Hierarchical Behavioral Test Generator (HBTG) and Modeler's Assistant, forms a part of the Automatic Test Generation System being developed at Virginia Tech. The PTG software transforms the VHDL description of a circuit, given by Modeler's Assistant, into a Control Flow Graph (CFG) that describes the control and data flow information in the behavioral model. The process test generation algorithm, called the PTG algorithm, uses the CFG to generate stimulus/response test sets that test all the functions of the VHDL model. The algorithm creates events on signals, propagates these events and uses simulation to obtain responses. Various features present in the software like the generation of the Control Flow Graph, the PTG algorithm, and the construction of paths through the CFG to propagate and justify events, are discussed. The test sets generated by PTG can be used for the hierarchical test generation by HBTG, which was developed earlier. Another program, called Test Bench Generator (TBG), is presented in this thesis. It is used to convert the test sequence generated by HBTG into a VHDL Test Bench that can be used for simulation. / Master of Science

Approved for public release, distribution is unlimited / This thesis discusses VHDL modeling and simulation of a full custom Application Specific Integrated Circuit (ASIC) for a Digital Image Synthesizer (DIS). The DIS synthesizes the characteristic echo signature of a pre-selected target. It is mainly used against Inverse Synthetic Aperture Radars as an electronic counter measure. The VHDL description of the DIS architecture was exported from Tanner S-Edit, modified, and simulated in Aldec Active HDLTM. Simulation results were compared with C++ and Matlab simulation results for verification. Main subcomponents, a single Range Bin Processor (RBP), a cascade of 4 RBP s and a cascade of 16 RBP s were tested and verified. The overhead control circuitry, including Self Test Circuitry and Phase Extractor, was tested separately. Finally overall DIS was tested and verified using the control circuitry and a cascade of 4 RBP s together, representing the actual 512 RBP s. As a result of this research, the majority of the DIS was functionally tested and verified. / First Lieutenant, Turkish Army