In mobile robot applications, it is an important issue for a robot to know where it is. Accurate localization becomes crucial for navigation and map building applications because both route to follow and positions of the objects to be inserted into the map highly depend on the position of the robot in the environment. For localization, the robot uses the measurements that it takes by various devices such as laser rangefinders, sonars, odometry devices and vision. Generally these devices give the distances of the objects in the environment to the robot and proceesing these distance information, the robot finds its location in the environment. In this thesis, two vision-based robot localization algorithms are implemented. The first algorithm uses artificial landmarks as the objects around the robot and by measuring the positions of these landmarks with respect to the camera system, the robot locates itself in the environment. Locations of these landmarks are known. The second algorithm instead of using artificial landmarks, estimates its location by measuring the positions of the objects that naturally exist in the environment. These objects are treated as natural landmarks and locations of these landmarks are not known initially. A three-wheeled robot base on which a stereo camera system is mounted is used as the mobile robot unit. Processing and control tasks of the system is performed by a stationary PC. Experiments are performed on this robot system. The stereo camera system is the measurement device for this robot.

In this thesis, an intelligent controller architecture for gait selection of a serpentine robot intended to be used in search and rescue tasks is designed, developed and simulated. The architecture is independent of the configuration of the robot and the robot is allowed to make different kind of movements, similar to grasping. Moreover, it is applicable to parallel processing in several aspects and it is an implementation of a controller network on robot segment network. In the architecture several behaviors are defined for each of the segments. Every behavior is realized in the form of Fuzzy Actor-Critic Learning agents based on fuzzy networks and reinforcement learning. Each segment controller determines the next suitable position in the sensory space acquired using ultrasound sensors, a genetic algorithm implementation then tries to find the change of the joint angles to achieve the desired movement in a given amount of time. This allows optimization on different criteria, during motion. Simulations are performed and presented to introduce the efficiency of the developed controller architecture. Moreover a simplified mathematical analysis is performed to gain insight of the controller dynamics.

The popularity of e-commerce sites and applications that use recommendations and user modeling is increased recently. The development and contest in tourism calls attention of large-scale IT companies. These companies have started to work on recommendation systems and user modeling on tourism sector. Some of the clustering methodologies, neighboring methods and machine learning algorithms are commenced to use for making predictions about tourist&rsquo / s interests while he/she is traveling around the city. Recommendation ability is the most interesting thing for a tourist guide application. Recommender systems are composed of two main approaches, collaborative and content-based filtering. Collaborative filtering algorithms look for people that have similar interests and properties, while contentbased filtering methods pay attention to sole user&rsquo / s interests and properties to make recommendations. Both of the approaches have advantages and disadvantages, for that reason sometimes these two approaches are used together. Chosen method directly affects the recommendation quality, so advantages and disadvantages of both methods will be examined carefully. Recommendation of locations or services can be seen as a classification problem. Artificial intelligent systems like neural networks, genetic algorithms, particle swarm optimization algorithms, artificial immune systems are inspired from natural life and can be used as classifier systems. Artificial immune system, inspired from human immune system, has ability to classify huge numbers of different patterns. In this paper ESGuide, a tourist guide application that uses artificial immune system is examined. ESGuide application is a client-server application that helps tourists while they are traveling around the city. ESGuide has two components: Map agent and recommender agent. Map agent helps the tourist while he/she interacts with the city map. Tourist should rate the locations and items while traveling. Due to these ratings and client-server interaction, recommender agent tries to predict user interested places and items. Tourist has a chance to state if he/she likes the recommendation or not. If the tourist does not like the recommendation, new recommendation set is created and presented to the user.

Neste trabalho de pesquisa, foi realizado um estudo dos principais tipos de ferramentas para modelagem de hardware buscando-se verificar as vantagens da utilização de Redes de Petri para a modelagem de sistemas dinâmicos e concorrentes e de sua implementação em hardware. Observou-se que apesar de existirem ferramentas para esta finalidade, existem pontos que podem ser trabalhados para facilitar o acesso a esta tecnologia. Assim, foi desenvolvido um método para facilitar a implementação de sistemas modelados em Redes de Petri, em hardware de lógica reconfigurável. Para isto, utilizou-se um software de captura onde, a partir do gráfico do modelo em Rede de Petri, é gerado um arquivo de descrição no formato PNML - Linguagem de Marcação para Rede de Petri (Petri Net Markup Language). A partir desta descrição, é gerado um arquivo de descrição de hardware no formato VHDL - Linguagem de Descrição de Hardware VHSIC (VHSIC Hardware Description Language), que pode ser gravado em um circuito de lógica reconfigurável. Para possibilitar esta etapa, foi realizado o desenvolvimento de uma ferramenta que gera um arquivo em linguagem VHDL a partir da descrição no formato PNML. A ferramenta desenvolvida é descrita em detalhes, mostrando todas as etapas e critérios utilizados na conversão. Para validar o método, é mostrado um exemplo de aplicação com a implementação em FPGA - Matriz de Portas Programável em Campo (Field Programmable Gate Arrow), de uma Rede de Petri modelando uma planta industrial hipotética. Finalmente é feita uma comparação de desempenho entre o modelo executado em hardware com o modelo executado em software. / In this research work, was performed a study of main types of hardware modeling tools searching to verify the advantages of utilizing for modeling dynamic and concurrent systems and for its hardware implementation. It was observed that even though there are tools for this purpose, exists some points that may be worked out to facilitate access to this technology. So, was developed a method for facilitate implementation of systems modeled in Petri nets, in reconfigurable logic hardware. For that, was utilized a capture software where, from the graphic of the Petri net model, is generated a description in PNML (Petri Net Markup Language) format. From this description, is generated a hardware description file in VHDL (VHSIC Hardware Description Language) format, that may be loaded in a reconfigurable logic circuit. To make possible this stage, was performed the development of tool that generate a file in VHDL language from the description in PNML format. The developed tool is described in details, showing all stages and criteria utilized in the conversion. To validate the method, is showed an application example for this toll with the implementation in FPGA (Field Programmable Gate Arrow), of a Petri net modeling a hypothetic industrial plant. Finally, a performance comparison is made between the model executed in hardware and the model executed in software.

Neste trabalho de pesquisa, foi realizado um estudo dos principais tipos de ferramentas para modelagem de hardware buscando-se verificar as vantagens da utilização de Redes de Petri para a modelagem de sistemas dinâmicos e concorrentes e de sua implementação em hardware. Observou-se que apesar de existirem ferramentas para esta finalidade, existem pontos que podem ser trabalhados para facilitar o acesso a esta tecnologia. Assim, foi desenvolvido um método para facilitar a implementação de sistemas modelados em Redes de Petri, em hardware de lógica reconfigurável. Para isto, utilizou-se um software de captura onde, a partir do gráfico do modelo em Rede de Petri, é gerado um arquivo de descrição no formato PNML - Linguagem de Marcação para Rede de Petri (Petri Net Markup Language). A partir desta descrição, é gerado um arquivo de descrição de hardware no formato VHDL - Linguagem de Descrição de Hardware VHSIC (VHSIC Hardware Description Language), que pode ser gravado em um circuito de lógica reconfigurável. Para possibilitar esta etapa, foi realizado o desenvolvimento de uma ferramenta que gera um arquivo em linguagem VHDL a partir da descrição no formato PNML. A ferramenta desenvolvida é descrita em detalhes, mostrando todas as etapas e critérios utilizados na conversão. Para validar o método, é mostrado um exemplo de aplicação com a implementação em FPGA - Matriz de Portas Programável em Campo (Field Programmable Gate Arrow), de uma Rede de Petri modelando uma planta industrial hipotética. Finalmente é feita uma comparação de desempenho entre o modelo executado em hardware com o modelo executado em software. / In this research work, was performed a study of main types of hardware modeling tools searching to verify the advantages of utilizing for modeling dynamic and concurrent systems and for its hardware implementation. It was observed that even though there are tools for this purpose, exists some points that may be worked out to facilitate access to this technology. So, was developed a method for facilitate implementation of systems modeled in Petri nets, in reconfigurable logic hardware. For that, was utilized a capture software where, from the graphic of the Petri net model, is generated a description in PNML (Petri Net Markup Language) format. From this description, is generated a hardware description file in VHDL (VHSIC Hardware Description Language) format, that may be loaded in a reconfigurable logic circuit. To make possible this stage, was performed the development of tool that generate a file in VHDL language from the description in PNML format. The developed tool is described in details, showing all stages and criteria utilized in the conversion. To validate the method, is showed an application example for this toll with the implementation in FPGA (Field Programmable Gate Arrow), of a Petri net modeling a hypothetic industrial plant. Finally, a performance comparison is made between the model executed in hardware and the model executed in software.

This diploma thesis studies teaching of computer hardware with it's main goal set in evaluation of the topic's benefit in curriculum of grammar schools. Key aspects of evaluation are relation of topic to the rest of ICT curriculum and other school subjects, background in relevant curricular documents of Czech republic, students' attitude and expectations in regard of the topic determined by survey and comparison of schools' curriculum to topic's structure in literature. Main outcomes are determination of actual form of teaching computer hardware at grammar schools and recommending way of further development thereof regarding students' needs and motivation and variability of teaching methods available. Keywords ICT, Computer hardware, curriculum, teaching methods, curricular documents, pupil's attitude, motivation

<p>The technology availability and hype of virtual reality has intersected as of 2016, bringing a lot of attention to virtual reality (VR) games. The research into this technology has been ongoing since its early exploration in the 1970’s. Methods have been created to try to understand and predict what causes phenomena such as motion and simulator sickness in the human computer interaction devices. Heuristics have been developed to aid the design these applications and to avoid such discomforting circumstances. Concepts and their continued exploration have been growing to improve the experience of virtual reality technology and continue the expanding imagination of what is capable with this technology. All the tools are available to create highly immersive virtual experiences, but it is up to the interpretant, the user to decide how believable, immersive and enjoyable these experiences are. By conducting an interview study on a part of the VR gaming community, more can be understood about the success and failure of immersive design by exploring the experiences of certain highly immersive games. This study takes the opportunity to listen to gamers as a means of highlighting significant key challenges and characteristics creating immersive VR games. By evaluating transcripts via thematic analysis, themes were created to understand and categorize the various aspects that are most important to the immersion and embodiment in VR games. This study and themes drawn from it reflect on the experiences and feelings of experienced VR gamers in the context of role-playing games.</p>

<div>Machine Learning (ML) workloads, being memory and compute-intensive, consume large amounts of power running on conventional computing systems, restricting their implementations to large-scale data centers. Thus, there is a need for building domain-specific hardware primitives for energy-efficient ML processing at the edge. One such approach is in-memory computing, which eliminates frequent and unnecessary data-transfers between the memory and the compute units, by directly computing the data where it is stored. Most of the chip area is consumed by on-chip SRAMs in both conventional von-Neumann systems (e.g. CPU/GPU) as well as application-specific ICs (e.g. TPU). Thus, we propose various circuit techniques to enable a range of computations such as bitwise Boolean and arithmetic computations, binary convolution operations, non-Boolean dot-product operations, lookup-table based computations, and spiking neural network implementation - all within standard SRAM memory arrays.</div><div><br></div><div>First, we propose X-SRAM, where, by using skewed sense amplifiers, bitwise Boolean operations such as NAND/NOR/XOR/IMP etc. can be enabled within 6T and 8T SRAM arrays. Moreover, exploiting the decoupled read/write ports in 8T SRAMs, we propose read-compute-store scheme where the computed data can directly be written back in the array simultaneously. </div><div><br></div><div>Second, we propose Xcel-RAM, where we show how binary convolutions can be enabled in 10T SRAM arrays for accelerating binary neural networks. We present charge sharing approach for performing XNOR operations followed by a population count (popcount) using both analog and digital techniques, highlighting the accuracy-energy tradeoff. </div><div><br></div><div>Third, we take this concept further and propose CASH-RAM, to accelerate non-Boolean operations, such as dot-products within standard 8T-SRAM arrays by utilizing the parasitic capacitances of bitlines and sourcelines. We analyze the non-idealities that arise due to analog computations and propose a self-compensation technique which reduces the effects of non-idealities, thereby reducing the errors. </div><div><br></div><div>Fourth, we propose ROM-embedded caches, RECache, using standard 8T SRAMs, useful for lookup-table (LUT) based computations. We show that just by adding an extra word-line (WL) or a source-line (SL), the same bit-cell can store a ROM bit, as well as the usual RAM bit, while maintaining the performance and area-efficiency, thereby doubling the memory density. Further we propose SPARE, an in-memory, distributed processing architecture built on RECache, for accelerating spiking neural networks (SNNs), which often require high-order polynomials and transcendental functions for solving complex neuro-synaptic models. </div><div><br></div><div>Finally, we propose IMPULSE, a 10T-SRAM compute-in-memory (CIM) macro, specifically designed for state-of-the-art SNN inference. The inherent dynamics of the neuron membrane potential in SNNs allows processing of sequential learning tasks, avoiding the complexity of recurrent neural networks. The highly-sparse spike-based computations in such spatio-temporal data can be leveraged for energy-efficiency. However, the membrane potential incurs additional memory access bottlenecks in current SNN hardware. IMPULSE triew to tackle the above challenges. It consists of a fused weight (WMEM) and membrane potential (VMEM) memory and inherently exploits sparsity in input spikes. We propose staggered data mapping and re-configurable peripherals for handling different bit-precision requirements of WMEM and VMEM, while supporting multiple neuron functionalities. The proposed macro was fabricated in 65nm CMOS technology. We demonstrate a sentiment classification task from the IMDB dataset of movie reviews and show that the SNN achieves competitive accuracy with only a fraction of trainable parameters and effective operations compared to an LSTM network.</div><div><br></div><div>These circuit explorations to embed computations in standard memory structures shows that on-chip SRAMs can do much more than just store data and can be re-purposed as on-demand accelerators for a variety of applications. </div>

In power distribution system planning, it is essential to understand the impacts that electric vehicles (EVs), and the non-linear, time-variant loading profiles associated with their charging units, may have on power distribution networks. This research presents a design methodology for the creation of both analytical and behavioral models for EV charging units within a VHDL-AMS simulation environment. Voltage and current data collected from Electric Avenue, located on the Portland State University campus, were used to create harmonic profiles of the EV charging units at the site. From these profiles, generalized models for both single-phase (Level 2) and three-phase (Level 3) EV chargers were created. Further, these models were validated within a larger system context utilizing the IEEE 13-bus distribution test feeder system. Results from the model's validation are presented for various charger and power system configurations. Finally, an online tool that was created for use by distribution system designers is presented. This tool can aid designers in assessing the impacts that EV chargers have on electrical assets, and assist with the appropriate selection of transformers, conductor ampacities, and protection equipment & settings.

In this thesis, a service oriented decomposition approach: Use case Driven Service Oriented Architecture (UDSOA), is introduced to close the gap between business requirements and SOA (Service Oriented Architecture) design by including business use cases and system use cases into decomposition process. The approach is constructed upon Service Oriented Software Engineering (SOSE) modeling technique and aims to fill the deficits of it at the decomposition phase. Further, it aims to involve both business vision and Information Technologies concerns in the decomposition process. This approach starts with functional top-down decomposition of the domain. Then, business use cases are used for further decomposition because of their high-level view. This connects the business requirements and our SOA design. Also it raises the level of abstraction which allows us to focus on business services. Second step of the SOA approach uses system use cases to continue decomposition. System use cases help discovering technical web services and allocating them on the decomposition tree. Service oriented analysis also helps separating business and technical services in tightly coupled architecture conditions. Those two steps together bring quality in to both problem and solution domains.