Multiple-centered clustering method and decision making system algorithm on menopause data set depending on multiple-centered clustering are described in this study. This method consists of two stages. At the first stage, fuzzy C-means (FCM) clustering algorithm is applied on the data set under consideration with a high number of cluster centers. As the output of FCM, cluster centers and membership function values for each data member is calculated. At the second stage, original cluster centers obtained in the first stage are merged till the new numbers of clusters are reached. Merging process relies upon a &ldquo / similarity measure&rdquo / between clusters defined in the thesis. During the merging process, the cluster center coordinates do not change but the data members in these clusters are merged in a new cluster. As the output of this method, therefore, one obtains clusters which include many cluster centers. In the final part of this study, an application of the clustering algorithms &ndash / including the multiple centered clustering method &ndash / a decision making system is constructed using a special data on menopause treatment. The decisions are based on the clusterings created by the algorithms already discussed in the previous chapters of the thesis. A verification of the decision making system / v decision aid system is done by a team of experts from the Department of Department of Obstetrics and Gynecology of Hacettepe University under the guidance of Prof. Sinan Beksa&ccedil / .

The Dynamic Distributed Dependable Real-Time Industrial communication Protocol (D3RIP) provides service guarantees for Real-Time traffic and integrates the dynamically changing requirements of automation applications in their operation to efficiently utilize the resources. The protocol dynamically allocates the network resources according to the respective system state. To this end, the protocol architecture consists of an Interface Layer that provides time-slotted operation and a Coordination Layer that assigns each time slot to a unique transmitter device based on a distributed computation. In this thesis, a software simulator for D3RIP is developed. Using the D3RIP Simulator, modifications in D3RIP can be easily examined without facing complexities in real implementations and extensive effort in terms of time and cost. The simulator simulates the Interface Layer, the Coordination Layer and additionally, the Shared Medium. Hence, using the simulator, the system-protocol couple can be easily analyzed, tested and further improvements on D3RIP can be achieved with the least amount of effort. The simulator implements the Timed Input Output Automata (TIOA) models of the D3RIP stack components using C++. The resulting code is compiled on GCC (Gnu Compiler Collection). The logs of the simulation runs and the real system with 2 devices connected via cross 100MbE cables are compared. In a 3ms time slot, the simulator and the system incidents differ about 135&micro / s on the average, causing no asynchronousity in their instantaneous operational states. The D3RIP Simulator is useful in keeping track of any variable in the D3RIP system automaton at any instant up to 1&micro / s resolution.

Existem máquinas que necessitam de uma grande velocidade de processamento para seu correto trabalho, essas máquinas possuem um tempo de processamento de resposta crítico. Quando considera-se este aspecto somado à necessidade de um controle do comportamento estático e dinâmico de um sistema chega-se ao controlador com fortes demandas de tempo de execução. Essa dissertação compara controladores discretos implementados em ponto fixo, com diferentes precisões, usando para tanto a simulação do comportamento de controladores confeccionados em linguagem de comandos Matlab e em linguagem VHDL 2008. Esta última está em desenvolvimento e padronização pelo IEEE. A linguagem VHDL é usada nas FPGAs que são dispositivos de alta velocidade e capacidade de processamento paralelo. O principal objetivo do trabalho é o estudo e a implementação de controladores discretos em FPGA com o auxílio da linguagem VHDL 2008, determinando suas virtudes e limitações, em particular quanto à estrutura de programação, análise de erro e a demanda por recursos. Os resultados alcançados demonstram que algumas melhorias ainda precisam ser feitas para que o VHDL 4.0, conhecido como VHDL 2008, seja entregue ao mercado como padrão estável. Entretanto, quando conhecidas suas limitações, já é possível seu uso em implementações com conversão de sinais discretos para analógicos, como é o caso de controle e simulação de sistemas dinâmicos como servomecanismos. / There are machines that need large processing speed for its correct working, these machines have a critical time response processing. When it is considered that aspect coupled with the need for control of static and dynamic behavior of a system arrives at the controller with strong demands on runtime. This dissertation compares discrete controllers implemented in fixed point with different accuracies, using for both the simulation of the behavior of controllers manufactured in Matlab command language and VHDL 2008. VHDL 2008 still in development and standardization by the IEEE. The VHDL language is used in FPGAs that are high speed devices with parallel processing capability. The main objective of this work is the study and implementation of discrete controllers in FPGA with the help of the VHDL 2008 language, determining its strengths and limitations, particularly in regard to the structure of programming, error analysis and demand for resources. Results show that accuracy still need some improvements a standard to the VHDL 4.0, known as VHDL 2008, is delivered to the market a stable standard. However, knowing it limitations, it is possible implementations and use in conversion of analog signals to discrete, such as control and dynamic systems simulation like servomechanisms.

Este trabalho apresenta a modelagem e implementação em FPGA de sistemas digitais de compensação de desvios para TIADC. O desenvolvimento de todo este trabalho seguiu uma metodologia top-down. Seguindo esta metodologia foi elaborada a modelagem comportamental de um TIADC de dois canais e seus respectivos desvios de offset, ganho e clock skew em Simulink. Além da modelagem comportamental de sistemas digitais para a compensação destes desvios. Para o desvio de clock skew foi utilizada a compensação através de filtros de delay fracionário, mais especificamente, a eficiente estrutura de Farrow. A definição de qual método seria utilizado para o projeto do filtro, e da estrutura de Farrow, exigiu um estudo de diversos métodos de projeto apresentados na literatura. Os sistemas digitais de compensação modelados foram convertidos em código VHDL, para implementação e validação em FPGA. A validação destes sistemas foi realizada utilizando a metodologia de teste FPGA In Loop. Os resultados obtidos com os compensadores de desvio do TIADC demonstram o elevado ganho de desempenho fornecido por estas estruturas. Além deste resultado, este trabalho ilustra o potencial das metodologias de desenvolvimento, implementação e teste em FPGA utilizadas para a obtenção destes compensadores. / This work presents the modeling and FPGA implementation of digital TIADC mismatches compensation systems. The development of the whole work follows a top-down methodology. Following this methodology was developed a two channel TIADC behavior modeling and their respective offset, gain and clock skew mismatches on Simulink. In addition was developed digital mismatch compensation system behavior modeling. For clock skew mismatch compensation fractional delay filters were used, more specifically, the efficient Farrow struct. The definition of wich filter design methodology would be used, and wich Farrow structure, required the study of various design methods presented in literature. The digital compensation systems models were converted to VHDL, for FPGA implementation and validation. These system validation was carried out using the test methodology FPGA In Loop . The results obtained with TIADC mismatch compensators show the high performance gain provided by these structures. Beyond this result, these work illustrates the potential of design, implementation and FPGA test methodologies.

Este trabalho apresenta a modelagem e implementação em FPGA de sistemas digitais de compensação de desvios para TIADC. O desenvolvimento de todo este trabalho seguiu uma metodologia top-down. Seguindo esta metodologia foi elaborada a modelagem comportamental de um TIADC de dois canais e seus respectivos desvios de offset, ganho e clock skew em Simulink. Além da modelagem comportamental de sistemas digitais para a compensação destes desvios. Para o desvio de clock skew foi utilizada a compensação através de filtros de delay fracionário, mais especificamente, a eficiente estrutura de Farrow. A definição de qual método seria utilizado para o projeto do filtro, e da estrutura de Farrow, exigiu um estudo de diversos métodos de projeto apresentados na literatura. Os sistemas digitais de compensação modelados foram convertidos em código VHDL, para implementação e validação em FPGA. A validação destes sistemas foi realizada utilizando a metodologia de teste FPGA In Loop. Os resultados obtidos com os compensadores de desvio do TIADC demonstram o elevado ganho de desempenho fornecido por estas estruturas. Além deste resultado, este trabalho ilustra o potencial das metodologias de desenvolvimento, implementação e teste em FPGA utilizadas para a obtenção destes compensadores. / This work presents the modeling and FPGA implementation of digital TIADC mismatches compensation systems. The development of the whole work follows a top-down methodology. Following this methodology was developed a two channel TIADC behavior modeling and their respective offset, gain and clock skew mismatches on Simulink. In addition was developed digital mismatch compensation system behavior modeling. For clock skew mismatch compensation fractional delay filters were used, more specifically, the efficient Farrow struct. The definition of wich filter design methodology would be used, and wich Farrow structure, required the study of various design methods presented in literature. The digital compensation systems models were converted to VHDL, for FPGA implementation and validation. These system validation was carried out using the test methodology FPGA In Loop . The results obtained with TIADC mismatch compensators show the high performance gain provided by these structures. Beyond this result, these work illustrates the potential of design, implementation and FPGA test methodologies.

Die "Mitteilungen des URZ" informieren die Nutzer des Universitätsrechenzentrums der TU Chemnitz umfassend über neue Dienste und Projekte, vermitteln ggf. Hintergrundwissen und dienen der Berichterstattung.

Today’s embedded systems depend on the availability of hybrid platforms, that contain heterogeneous computing resources such as programmable processors units (CPU’s or DSP’s) and highly specialized hardware cores. These platforms have been scaled down to integrated embedded system-on-chip. Modern platform FPGAs enhance such systems by the flexibility of runtime configurable silicon. One of the major advantages that arises is the ability to use hardware (HW) and software (SW) resources in a time-shared manner. Though the ability to dynamically assign computing resources based on decisions taken at runtime is given.

<div>The ‘Internet of Things’ has increased the demand for artificial intelligence (AI)-based edge computing in applications ranging from healthcare monitoring systems to autonomous vehicles. However, the growing complexity of machine learning workloads requires rethinking to make AI amenable to resource constrained environments such as edge devices. To that effect, the entire stack of machine learning, from algorithms to hardware primitives, have been explored to enable energy-efficient intelligence at the edge. </div><div><br></div><div>From the algorithmic aspect, model compression techniques such as quantization are powerful tools to address the growing computational cost of ML workloads. However, quantization, particularly, can result in substantial loss of performance for complex image classification tasks. To address this, a principal component analysis (PCA)-driven methodology to identify the important layers of a binary network, and design mixed-precision networks. The proposed Hybrid-Net achieves a significant improvement in classification accuracy over binary networks such as XNOR-Net for ResNet and VGG architectures on CIFAR-100 and ImageNet datasets, while still achieving up remarkable energy-efficiency. </div><div><br></div><div>Having explored compressed neural networks, there is a need to investigate suitable computing systems to further the energy efficiency. Memristive crossbars have been extensively explored as an alternative to traditional CMOS based systems for deep learning accelerators due to their high on-chip storage density and efficient Matrix Vector Multiplication (MVM) compared to digital CMOS. However, the analog nature of computing poses significant issues due to various non-idealities such as: parasitic resistances, non-linear I-V characteristics of the memristor device etc. To address this, a simplified equation-based modelling of the non-ideal behavior of crossbars is performed and correspondingly, a modified technology aware training algorithm is proposed. Building on the drawbacks of equation-based modeling, a Generalized Approach to Emulating Non-Ideality in Memristive Crossbars using Neural Networks (GENIEx) is proposed where a neural network is trained on HSPICE simulation data to learn the transfer characteristics of the non-ideal crossbar. Next, a functional simulator was developed which includes key architectural facets such as tiling, and bit-slicing to analyze the impact of non-idealities on the classification accuracy of large-scale neural networks.</div><div><br></div><div>To truly realize the benefits of hardware primitives and the algorithms on top of the stack, it is necessary to build efficient devices that mimic the behavior of the fundamental units of a neural network, namely, neurons and synapses. However, efforts have largely been invested in implementations in the electrical domain with potential limitations of switching speed, functional errors due to analog computing, etc. As an alternative, a purely photonic operation of an Integrate-and-Fire Spiking neuron is proposed, based on the phase change dynamics of Ge2Sb2Te5 (GST) embedded on top of a microring resonator, which alleviates the energy constraints of PCMs in electrical domain. Further, the inherent parallelism of wavelength-division multiplexing (WDM) was leveraged to propose a photonic dot-product engine. The proposed computing platform was used to emulate a SNN inferencing engine for image-classification tasks. These explorations at different levels of the stack can enable energy-efficient machine learning for edge intelligence. </div><div><br></div><div>Having explored various domains to design efficient DNN models and studying various hardware primitives based on emerging technologies, we focus on Silicon implementation of compute-in-memory (CIM) primitives for machine learning acceleration based on the more available CMOS technology. CIM primitives enable efficient matrix-vector multiplications (MVM) through parallelized multiply-and-accumulate operations inside the memory array itself. As CIM primitives deploy bit-serial computing, the computations are exposed bit-level sparsity of inputs and weights in a ML model. To that effect, we present an energy-efficient sparsity-aware reconfigurable-precision compute-in-memory (CIM) 8T-SRAM macro for machine learning (ML) applications. Standard 8T-SRAM arrays are re-purposed to enable MAC operations using selective current flow through the read-port transistors. The proposed macro dynamically leverages workload sparsity by reconfiguring the output precision in the peripheral circuitry without degrading application accuracy. Specifically, we propose a new energy-efficient reconfigurable-precision SAR ADC design with the ability to form (n+m)-bit precision using n-bit and m-bit ADCs. Additionally, the transimpedance amplifier (TIA) –required to convert the summed current into voltage before conversion—is reconfigured based on sparsity to improve sense margin at lower output precision. The proposed macro, fabricated in 65 nm technology, provides 35.5-127.2 TOPS/W as the ADC precision varies from 6-bit to 2-bit, respectively. Building on top of the fabricated macro, we next design a hierarchical CIM core micro-architecture that addresses the existing CIM scaling challenges. The proposed CIM core micro-architecture consists of 32 proposed sparsity-aware CIM macros. The 32 macros are divided into 4 matrix-vector multiplication units (MVMUs) consisting of 8 macros each. The core has three unique features: i) it can adaptively reconfigure ADC precision to achieve energy-efficiency and lower latency based on input and weight sparsity, determined by a sparsity controller, ii) it deploys row-gating feature to maintain SNR requirements for accurate DNN computations, and iii) hardware support for load balancing to balance latency mismatches occurring due to different ADC precisions in different compute units. Besides the CIM macros, the core micro-architecture consists of input, weight, and output memories, along with instruction memory and control circuits. The instruction set architecture allows for flexible dataflows and mapping in the proposed core micro-architecture. The sparsity-aware processing core is scheduled to be taped out next month. The proposed CIM demonstrations complemented by our previous analysis on analog CIM systems progressed our understanding of this emerging paradigm in pertinence to ML acceleration.</div>

Conselho Nacional do Desenvolvimento Científico e Tecnológico (CNPq) / É implementado em hardware, por meio da linguagem VHDL, um método de avaliação objetiva de qualidade de vídeo digital. Sendo um processo computacionalmente custoso em software, investiga-se sua implementação em hardware. O método implementado, chamado de NRVQA-LM, utiliza seis características espaço-temporais extraídas de diferentes vídeos para chegar a um escore de qualidade. São estudadas essas características e planejada a sua implementação de forma otimizada, a fim de aproveitar as vantagens de plataformas de lógica reconfigurável, como as FPGAS. Durante o desenvolvimento foi necessário o estudo de ferramentas não usuais da linguagem VHDL, tais como as aritméticas de ponto fixo e flutuante e a escrita de funções matemáticas. Os resultados mostram alta correlação com os valores das características e dos escores de qualidade em relação ao método em software. A implementação se mostrou custosa em termos de recursos lógicos, especialmente devido à necessidade de se armazenar um quadro de vídeo inteiro, mas eficiente graças à característica de paralelismo das FPGAs, executando cálculos entre 20 e 40 vezes mais rapidamente que em uma linguagem de alto nível como o MATLAB. A aritmética ponto fixo mostrou-se vantajosa em relação ao ponto flutuante, principalmente no que tange à frequência de operação. / It is implemented in hardware an objective digital video evaluation method, using the VHDL language. As a computationally expensive process in software, it is investigated its implementation in a hardware platform. The implemented method, named NRVQA-LM, employs six spatio-temporal features extracted from different videos in order to obtain a quality score. These features are studied and the implementation is designed to be developed in an optimized way, in order to explore the benefits of reprogammable logic platforms, such as FPGAs. During the development it was necessary to study non-recurrent tools of the VHDL language, such as fixed- and floating-point arithmetics and the writing of math functions. Results shows high correlation between the calculated scores of the hardware and the original software implementations. The hardware implementation revealed to be highly resource expensive, mainly due the need of storing a whole video frame, but efficient in time, thanks to the parallelism feature of FPGA devices, executing quality score calculations between 20 and 40 times faster than a high-level language such as MATLAB. The fixed-point arithmetics revealed to be more efficient than the floating-point, specially regarding operation frequency.

Conselho Nacional do Desenvolvimento Científico e Tecnológico (CNPq) / É implementado em hardware, por meio da linguagem VHDL, um método de avaliação objetiva de qualidade de vídeo digital. Sendo um processo computacionalmente custoso em software, investiga-se sua implementação em hardware. O método implementado, chamado de NRVQA-LM, utiliza seis características espaço-temporais extraídas de diferentes vídeos para chegar a um escore de qualidade. São estudadas essas características e planejada a sua implementação de forma otimizada, a fim de aproveitar as vantagens de plataformas de lógica reconfigurável, como as FPGAS. Durante o desenvolvimento foi necessário o estudo de ferramentas não usuais da linguagem VHDL, tais como as aritméticas de ponto fixo e flutuante e a escrita de funções matemáticas. Os resultados mostram alta correlação com os valores das características e dos escores de qualidade em relação ao método em software. A implementação se mostrou custosa em termos de recursos lógicos, especialmente devido à necessidade de se armazenar um quadro de vídeo inteiro, mas eficiente graças à característica de paralelismo das FPGAs, executando cálculos entre 20 e 40 vezes mais rapidamente que em uma linguagem de alto nível como o MATLAB. A aritmética ponto fixo mostrou-se vantajosa em relação ao ponto flutuante, principalmente no que tange à frequência de operação. / It is implemented in hardware an objective digital video evaluation method, using the VHDL language. As a computationally expensive process in software, it is investigated its implementation in a hardware platform. The implemented method, named NRVQA-LM, employs six spatio-temporal features extracted from different videos in order to obtain a quality score. These features are studied and the implementation is designed to be developed in an optimized way, in order to explore the benefits of reprogammable logic platforms, such as FPGAs. During the development it was necessary to study non-recurrent tools of the VHDL language, such as fixed- and floating-point arithmetics and the writing of math functions. Results shows high correlation between the calculated scores of the hardware and the original software implementations. The hardware implementation revealed to be highly resource expensive, mainly due the need of storing a whole video frame, but efficient in time, thanks to the parallelism feature of FPGA devices, executing quality score calculations between 20 and 40 times faster than a high-level language such as MATLAB. The fixed-point arithmetics revealed to be more efficient than the floating-point, specially regarding operation frequency.