It is my thesis that a cost-effective motion capture system for wireless 3D controllers can be developed through the use of low-cost inertial measurement devices and camera systems. Current optical motion capture systems require a number of expensive high-speed cameras. The use of such systems is impractical for many applications due to its high cost. This is particularly true for consumer-level wireless 3D controllers. More importantly, optical systems are capable of directly tracking an object with only three degrees of freedom. The proposed system attempts to solve these issues by combining a low-cost camera system with low-cost micro-machined inertial measurement devices such as accelerometers and gyro sensors to provide accurate motion tracking with a full six degrees of freedom. The proposed system combines the data collected from the various sensors in the system to obtain position information about the wireless 3D controller with 6 degrees of freedom. The system utilizes a number of calibration, error correction, and sensor fusion techniques to accomplish this task. The key advantage of the proposed system is that it combines the high long-term accuracy and low frequency nature of the camera system and complements it with the low long-term accuracy and high frequency nature of the inertial measurement devices to produce a system with a high level of long-term accuracy with detailed high frequency information about the motion of the wireless 3D controller.

Electricity systems are very complex systems and are composed of numerous transmission lines, generators and loads. The generating stations are generally far away from load centres and that may cause transmission line congestion and overloading. Series capacitive compensation is the most economical way to increase transmission capacity and improve transient stability of transmission grids. However, one of the impeding factors for the widespread use of series capacitive compensation is the potential risk of Subsynchronous Resonance (SSR). Subsynchronous Resonance is a phenomenon in which electrical power is exchanged with the generator shaft system in an increasing manner which may result in damage to the turbine generator shaft system. Therefore, mitigating SSR continues to be a subject of research and development aiming at developing effective SSR countermeasures.<p>This research work presents new methods of alleviating the SSR problem using a Static Synchronous Series Compensator (SSSC) and a Static Synchronous Compensator (STATCOM). These methods are based on using the SSSC and STATCOM to inject unbalanced series quadrature voltages and unbalanced shunt reactive currents in transmission line just after clearing faults. When the subsynchronous oscillations drive unsymmetrical phase currents, the developed electromagnetic torque will be lower than the condition when the three-phase currents are symmetrical. The unsymmetrical currents result in a lower coupling strength between the mechanical and the electrical system at asynchronous oscillations. Therefore, the energy exchange between the electrical and the mechanical systems at subsynchronous oscillations will be suppressed, thus, avoiding the build-up of torsional stresses on the generator shaft systems under subsynchronous resonance condition. The validity of proposed methods are demonstrated by time simulation results using the electromagnetic transient program EMTP-RV.

The thesis reports the results of comprehensive studies carried out to explore the impact of midpoint FACTS Controllers (STATCOM and SVC) on the generator distance phase backup protection in order to identify important issues that protection engineers need to consider when designing and setting a generator protection system. In addition, practical, feasible and simple solutions to mitigate the adverse impact of midpoint FACTS Controllers on the generator distance phase backup protection are explored. The results of these studies show that midpoint FACTS Controllers have an adverse effect on the generator distance phase backup protection. This adverse effect, which can be in the form of underreach, overreach or a time delay, varies according to the fault type, fault location and generator loading. Moreover, it has been found that the adverse effect of the midpoint FACTS Controllers extends to affect the coordination between the generator distance phase backup protection and the generator steady-state overexcited capability limit. The Support Vector Machines classification technique is proposed as a replacement for the existing generator distance phase backup protection relay in order to alleviate potential problems. It has been demonstrated that this technique is a very promising solution, as it is fast, reliable and has a high performance efficiency. This will result in enhancing the coordination between the generator phase backup protection and the generator steady-state overexcited capability limit in the presence of midpoint FACTS Controllers. The thesis also presents the results of investigations carried out to explore the impact of the generator distance phase backup protection relay on the generator overexcitation thermal capability. The results of these investigations reveal that with the relay settings according to the current standards, the generator is over-protected and the generator distance phase backup protection relay restricts the generator overexcitation thermal capability during system disturbances. This restriction does not allow the supply of the maximum reactive power of the generating unit during such events. The restriction on the generator overexcitation thermal capability caused by the generator distance phase backup protection relay highlights the necessity to revise the relay settings. The proposed solution in this thesis is to reduce the generator distance phase backup protection relay reach in order to provide secure performance during system disturbances.

Image generator host is the interface of the host computer systemof a flight simulator to its image generator. Image generator host, updates positions of the entities by sending operational codes to the image generator. Positional data of the entities is pipelined by tactic interface of the simulator at host update rate. A network jitter, latency, packet loss or inadequate bandwidth may disturb the smoothness of this pipelined entity information packets. This study presents an algorithm for the host system of a flight simulator, intending to minimize model flickering in the image generator display output.

Thesis--Auburn University, 2009. / Abstract. Vita. Includes MatLab code. Includes bibliography (p.43-44).

Thesis (Ph.D.)--Memorial University of Newfoundland, 2000. / Bibliography: leaves 179-191.

As semiconductor technology continues to scale lower in the nanometer era, the communication between processor and main memory has been particularly challenged. The well-studied frequency, memory and power ``walls'' have redirect architects towards utilizing Chip Multiprocessors (CMP) as an attractive architecture for leveraging technology scaling. In order to achieve high efficiency and throughput, CMPs rely heavily on sharing resources among multiple cores, especially in the case of the memory hierarchy. Unfortunately, such sharing introduces resource contention and interference between the multiple executing threads. The ever-increasing access latency difference between processor and memory, the gradually increasing memory bandwidth demands to main memory, and the decreasing cache capacity size available to each core due to multiple core integration, has made the need for an efficient memory subsystem resource management more critical than ever before. This dissertation focuses on managing the sharing of the Last-level Cache (LLC) capacity and the main memory bandwidth, as the two most important resources that significantly affect system performance and energy consumption. The presented schemes include efficient solutions to all of the three basic requirements for implementing a resource management schemes, that is: a) profiling mechanisms to capture applications' resource requirements, b) microarchitecture mechanisms to enforce a resource allocation scheme, and c) resource allocations algorithms/policies to manage the available memory resources throughput the whole memory hierarchy of a CMP system. To achieve these targets the dissertation first describes a set of low overhead, non-invasive profiling mechanisms that are able to project applications’ memory resource requirements and memory sharing behavior. Two memory resource partitioning schemes are presented. The first one, the Bank-aware dynamic partitioning scheme provides a low overhead solution for partitioning cache resources of large CMP architectures that are based on a Dynamic Non-Uniform Cache Architecture (DNUCA) last-level cache design, consistent with the current industry trends. In addition, the second scheme, the Bandwidth-aware dynamic scheme presents a system-wide optimization of memory-subsystem resource allocation and job scheduling for large, multi-chip CMP systems. The scheme is seeking for optimizations both within and outside single CMP chips, aiming at overall system throughput and efficiency improvements. As cache partitioning schemes with isolated partitions impose a set of restrictions in the use of the last-level cache, which can severely affect the performance of large CMP designs, this dissertation presents a Quasi-partitioning scheme that breaks such restrictions while providing most of the benefits of cache partitioning schemes. The presented solution is able to efficiently scale to a significant larger number of cores than what previously described schemes that are based on isolated partition can achieve. Finally, as the memory controller is one of the fundamental components of the memory-subsystem, a well-designed memory-subsystem resource management needs to carefully utilize the memory controller resources and coordinate its functionality with the operation of the main memory and the last-level cache. To improve execution fairness and system throughput, this dissertation presents a criticality-based, memory controller requests priority scheme. The scheme ranks demand read and prefetch operations based on their latency sensitivity, while it coordinates its operation with the DRAM page-mode policy and the memory data prefetcher. / text

M. Tech. Electrical engineering. / Discusses the process of standing from a chair is the first movement to be affected by physical impairment or ageing. That justified the increase of researches around sit-to-stand movements nowadays.This thesis presents the design of a four links wearable device that can assist disable people to stand from a sitting position. The four links are joined at the ankle, the knee and the HAT (Head, Arm and Trunk) where actuators are mounted. The system is built around three controllers. The Goal Controller drives the links along their reference trajectories, the Stability Controller makes sure that the system does not collapse as it is rising, and the last controller combines the signal from the 2 first ones.The reference trajectories are obtained from data recorded from healthy people performing the movement. The main idea behind the present design is that from seat off, the floor projection of the body centre of pressure is evaluated and compared to the most stable position. The stability controller generates the torque necessary to compensate the deviation, while the third controller adjusts the level of participation of that torque to satisfy both the trajectory and the stability objectives. Similar idea was previously found in Prinz (2010).

Can symmetry be utilized as a design principle to constrain evolutionary search, making it more effective? This dissertation aims to show that this is indeed the case, in two ways. First, an approach called ENSO is developed to evolve modular neural network controllers for simulated multilegged robots. Inspired by how symmetric organisms have evolved in nature, ENSO utilizes group theory to break symmetry systematically, constraining evolution to explore promising regions of the search space. As a result, it evolves effective controllers even when the appropriate symmetry constraints are difficult to design by hand. The controllers perform equally well when transferred from simulation to a physical robot. Second, the same principle is used to evolve minimal-size sorting networks. In this different domain, a different instantiation of the same principle is effective: building the desired symmetry step-by-step. This approach is more scalable than previous methods and finds smaller networks, thereby demonstrating that the principle is general. Thus, evolutionary search that utilizes symmetry constraints is shown to be effective in a range of challenging applications. / text

Η παρούσα διπλωματική αποτελεί την προσπάθεια κατασκευής ενός cache controller βασισμένο στον AHB BUS. Η ανάπτυξή του έγινε ως επί το πλείστο στο Εργαστήριο Vlsi του τμήματος Μηχανικών Υπολογιστών και Πληροφορικής με την προοπτική να ενσωματωθεί σε ένα ευρύτερο υπάρχων σύστημα βασισμένο στον open source cpu της arm Cortex M0. Δοκιμάστηκε επιτυχώς σε FPGA του εργαστηρίου αλλά ακόμα δεν έχει χρησιμοποιηθεί σε «πραγματικές συνθήκες». Απώτερος στόχος είναι να χρησιμοποιηθεί στο εργαστήριο για την επιτάχυνση εφαρμογών που θα χρειαστούν εξωτερική μνήμη δηλ. μεγαλύτερη μνήμη από την embedded του FPGA. Αν και δεν δοκιμάστηκε σε κάποιο άλλο σύστημα έχει φτιαχτεί με γνώμονα το πρότυπο του AHB οπότε υποθετικά δεν θα έχει κάποιο πρόβλημα να ενσωματωθεί σε οποιοδήποτε συμβατό με τον δίαυλο σύστημα. Η λογική πίσω από την υλοποίηση του είναι να είναι σχετικά εύκολη η αλλαγή ορισμένων μεταβλητών ώστε να διαφοροποιείται ο controller βάση των αναγκών του καθενός. Οι προδιαγραφές δίνονται παρακάτω αν και πιθανόν εκτός των πλαισίων της διπλωματικής και εντός του 2014 να επανα-σχεδιαστεί ώστε να γίνει πλήρως modular. / Cache controller compatible with AHB bus in system Verilog.