Sensor interfaces are needed to communicate the measured real-world analog values to the base¬band digital processor. They are dominated by the presence of high accuracy, high resolution analog to digital converters (ADC) in the backend. On most occasions, sensing is limited to small range measurements and low-modulation sensors where the complete dynamic range of ADC is not utilized. Designing a subsystem that integrates the sensor and the interface circuit and that works with a low resolution ADC requiring a small die-area is a challenge. In this work, we present a CMOS based area efficient, integrated sensor interface for applications like capacitance, temperature and dielectric-constant measurement. In addition, potential applica-tions for this work are in Cognitive Radios, Software Defined Radios, Capacitance Sensors, and location monitoring. The key contributions in the thesis are: 1 High Sensitivity Frequency-domain CMOS Capacitance Interface: A frequency domain capacitance interface system is proposed for a femto-farad capacitance measurement. In this technique, a ring oscillator circuit is used to generate a change in time period, due to a change in the sensor capacitance. The time-period difference of two such oscillators is compared and is read-out using a phase frequency detector and a charge pump. The output voltage of the system, is proportional to the change in the input sensor capacitance. It exhibits a maximum sensitivity of 8.1 mV/fF across a 300 fF capacitance range. 2 Sensitivity Enhancement for capacitance sensor: The sensitivity of an oscillator-based differential capacitance sensor has been improved by proposing a novel frequency domain capacitance-to-voltage (FDC) measurement technique. The capacitance sensor interface system is fabricated in a 130-nm CMOS technology with an active area of 0.17mm2 . It exhibits a maximum sensitivity of 244.8 mV/fF and a measurement resolution of 13 aF in a 10-100 fF measurement range, with a 10 pF nominal sensor capacitance and an 8-bit ADC. 3 Frequency to Digital Converter for Time/Distance measurement: A new architecture for a Vernier-based frequency-to-digital converter (VFDC) for location monitoring is pre¬sented, in which, a time interval measurement is performed with a frequency domain approach. Location monitoring is a common problem for many mobile robotic applica¬tions covering various domains, such as industrial automation, manipulation in difficult areas, rescue operations, environment exploration and monitoring, smart environments and buildings, robotic home appliances, space exploration and probing. The proposed architecture employs a new injection-locked ring oscillator (ILR) as the clock source. The proposed ILR oscillator does not need complex calibration procedures, usually required by Phase Locked Loop (PLL) based oscillators in Vernier-based time-to-digital convert¬ers. It consumes 14.4 µW and 1.15 mW from 0.4 V and 1.2 V supplies, respectively. The proposed VFDC thus achieves a large detectable range, fine time resolution, small die size and low power consumption simultaneously. The measured time-difference error is less than 50 ps at 1.2 V, enabling a resolution of 3 mm/kHz frequency shift. 4 A bio-sensor array for dielectric constant measurement: A CMOS on-chip sensor is presented to measure the dielectric constant of organic chemicals. The dielectric constant of these chemicals is measured using the oscillation frequency shift of a current controlled os¬cillator (CCO) upon the change of the sensor capacitance when exposed to the liquid. The CCO is embedded in an open-loop frequency synthesizer to convert the frequency change into voltage, which can be digitized using an off-chip analog-to-digital converter. The dielectric constant is then estimated using a detection procedure including the calibration of the sensor. 5 Integrated Temperature Sensor for thermal management: An integrated analog temper¬ature sensor which operates with simple, low-cost one-point calibration is proposed. A frequency domain technique to measure the on-chip silicon surface temperature, was used to measure the effects of temperature on the stability of a frequency synthesizer. The temperature to voltage conversion is achieved in two steps i.e. temperature to frequency, followed by frequency to voltage conversion. The output voltage can be used to com¬pensate the temperature dependent errors in the high frequency circuits, thereby reduc¬ing the performance degradation due to thermal gradient. Furthermore, a temperature measurement-based on-chip self test technique to measure the 3 dB bandwidth and the central frequency of common radio frequency circuits, was developed. This technique shows promise in performing online monitoring and temperature compensation of RF circuits.

<p>The last few decades have witnessed unprecedented growth in multiple areas of electronics spanning low-power sensing, intelligent computing and high-speed wireless connectivity. In the foreseeable future, there would be hundreds of billions of computing devices, sensors, things and people, wherein the technology will become intertwined with our lives through continuous interaction and collaboration between humans and machines. Such human-centric ideas give rise to the concept of internet of bodies (IoB), which calls for novel and energy-efficient techniques for sensing, processing and secure communication for resource-constrained IoB nodes.As we have painfully learnt during the pandemic, point-of-care diagnostics along with continuous sensing and long-term connectivity has become one of the major requirements in the healthcare industry, further emphasizing the need for energy-efficiency and security in the resource-constrained devices around us.</p> <p>  </p> <p>  With this vision in mind, I’ll divide this dissertation into the following chapters. The first part (Chapter 2) will cover time-domain sensing techniques which allow inherent energy-resolution scalability, and will show the fundamental limits of achievable resolution. Implementations will include 1) a radiation sensing system for occupational dosimetry in healthcare and mining applications, which can achieve 12-18 bit resolution with 0.01-1 µJ energy dissipation, and 2) an ADC-less neural signal acquisition system with direct Analog to Time Conversion at 13pJ/Sample. The second part (Chapters 3 and 4) of this dissertation will involve the fundamentals of developing secure energy-efficient electro-quasistatic (EQS) communication techniques for IoB wearables as well as implants, and will demonstrate  2 examples: 1) Adiabatic Switching for breaking the αCV^2f limit of power consumption in capacitive voltage mode human-body communication (HBC), and 2) Bi-Phasic Quasistatic Brain Communication (BP-QBC) for fully wireless data transfer from a sub-6mm^3, 2 µW brain implant. A custom modulation scheme, along with adiabatic communication enables wireline-like energy efficiencies (<5pJ/b) in HBC-based wireless systems, while the BP-QBC node, being fully electrical in nature, demonstrates sub-50pJ/b efficiencies by eliminating DC power consumption, and by avoiding the transduction losses observed in competing technologies, involving optical, ultrasound and magneto-electric modalities. Next in Chapter 5, we will show an implementation of a reconfigurable system that would include 1) a human-body communication transceiver and 2) a traditional wireless (MedRadio) transceiver on the same integrated circuit (IC), and would demonstrate methods to switch between the two modes by detecting the placement of the transmitter and receiver devices (on-body/away from the body). Finally, in Chapter 6, we shall show a technique of augmenting security in resource-constrained devices through authentication using the Analog/RF properties of the transmitter, which are usually discarded as non-idealities in a digital transceiver chain. This method does not require any additional hardware in the transmitter, making it an extremely promising technique to augment security in highly resource-constrained scenarios. Such energy-efficient intelligent sensing and secure communication techniques, when combined with intelligent in-sensor-analytics at the resource-constrained nodes, can potentially pave the way for perpetual, and even batteryless systems for next-generation IoT, IoB and healthcare applications.</p>

<p dir="ltr">This work will introduce a channel conceptualization and possible coding scheme for Graph-and-Symbol (GS) Communication. While Claude Shannon’s mathematical model for communication employed graphs to describe relationships and confusability among traditional time-sequenced signals, little work as been done to describe non-linear communication <i>with</i> graphs where we transmit and receive physical structures of information. The principal contribution of this work is to introduce a mathematical framework for communication with graphs which have symbols assigned to vertices. This looks like a molecule, and so we may think of these messages as coded forms of molecular communication.</p><p dir="ltr">At this time, many problems in this area will (and may remain) computationally intractable, but as the field of graph theory continues to develop, new tools and techniques may emerge to solve standing problems in this new subfield of communication.</p><p dir="ltr">Graphs present two difficulties: first, they contain ambiguities among their vertices and do not have an <i>a priori</i> canonical ordering, and second, the relationships among graphs lack structural regularities which we see in traditional error control coding lattices. There are no Galois fields to exploit over graph-based codes as we have with cyclic codes, for example. Furthermore, the shear number of graphs of order n grows so rapidly that it is difficult to account for the neighborhoods around codewords and effectively reduce communication errors which may occur. The more asymmetric a graph is, the more orderings on symbols it can support. However, asymmetries complicate the computation of channel transition probabilities, which are the cornerstone of all communication theory.</p><p dir="ltr">In the prologue, the reader will be introduced to a new educational tool for designing traditional binary cyclic codes.</p><p dir="ltr">1 through 10 will detail the development of Graph-and-Symbol (GS) Commu- nication to date followed by two example codes which demonstrate the power of structuring information on graphs.</p><p dir="ltr">Chapter 13 onward will review the preliminary work in another area of research, disjoint from the main body. It is included here for posterity and special interests in applying graphs to solving other problems in signal processing. It begins with an introduction of spacetime raythic graphs. We propose a new chamfering paradigm for connecting neighboring pixels which approximates solutions to the eikonal equation. We show that some raythic graphs possess structures with multiple, differing solutions to eikonal wavefront propagation which are essential to the construction of the Umbral Transform. This umbral transform emulates ray casting effects, such as shadows and diffraction within an image space, from a network-flow algorithm.</p><p dir="ltr">This work may be duplicated in whole or in part for educational purposes only. All other rights of this work are reserved by the author, Timothy Arthur Terlep Jr., of Rose-Hulman Institute of Technology, Terre Haute, IN (effective August 2024), and subject to the rules and regulations of the Graduate School of Purdue University.</p><p dir="ltr">Readers may contact the author with any comments and questions at <b>taterlep@gmail.com</b></p>