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  • About
  • The Global ETD Search service is a free service for researchers to find electronic theses and dissertations. This service is provided by the Networked Digital Library of Theses and Dissertations.
    Our metadata is collected from universities around the world. If you manage a university/consortium/country archive and want to be added, details can be found on the NDLTD website.
91

Adaptive and Robust Beam Selection in Millimeter-Wave Massive MIMO Systems

Khalili Marandi, Mostafa 05 June 2023 (has links)
Future 6G wireless communications network will increase the data capacity to unprecedented numbers and thus empower the deployment of new real-time applications. Millimeter-Wave (mmWave) band and Massive MIMO are considered as two of the main pillars of 6G to handle the gigantic influx in data traffic and number of mobile users and IoT devices. The small wavelengths at these frequencies mean that more antenna elements can be placed in the same area. Thereby, high spatial processing gains are achievable that can theoretically compensate for the higher isotropic path loss. The propagation characteristics at mmWave band, create sparse channels in typical scenarios, where only few paths convey significant power. Considering this feature, Hybrid (analog-digital) Beamforming introduces a new signal processing framework which enables energy and cost-efficient implementation of massive MIMO with innovative smart arrays. In this setup, the analog beamalignment via beam selection in link access phase, is the critical performance limiting step. Considering the variable operating condition in mmWave channels, a desirable solution should have the following features: efficiency in training (limited coherence time, delay constraints), adaptivity to channel conditions (large SNR range) and robustness to realized channels (LOS, NLOS, Multipath, non-ideal beam patterns). For the link access task, we present a new energy-detection framework based on variable length channel measurements with (orthogonal) beam codebooks. The proposed beam selection technique denoted as composite M-ary Sequential Competition Test (SCT) solves the beam selection problem when knowledge about the SNR operating point is not available. It adaptively changes the test length when the SNR varies to achieve an essentially constant performance level. In addition, it is robust to non-ideal beam patterns and different types of the realized channel. Compared to the conventional fixed length energy-detection techniques, the SCT can increase the training efficiency up to two times while reducing the delay if the channel condition is good. Having the flexibility to allocate resources for channel measurements through different beams adaptively in time, we improve the SCT to eliminate unpromising beams from the remaining candidate set as soon as possible. In this way, the Sequential Competition and Elimination Test (SCET) significantly further reduces training time by increasing the efficiency. The developed ideas can be applied with different codebook types considered for practical applications. The reliable performance of the beam selection technique is evident through experimental evaluation done using the state-of-the-art test-bed developed at the Vodafone Chair that combines a Universal Software Radio Peripheral (USRP) based platform with mmWave frontends.
92

Energieeffiziente integrierte Schaltungen zur Basisbandsignalverarbeitung und Zeitsynchronisation für drahtgebundene Ethernet-Echtzeitkommunikation

Buhr, Simon 28 January 2022 (has links)
In dieser Arbeit wird eine genaue Zeitsynchronisation über kupferbasierte Ethernetsysteme sowie der Entwurf von Schaltungen für die Bitübertragungsschicht (Physical Layer, PHY) in solchen Ethernetsystemen untersucht. Dabei wird der Entwurf eines integrierten Schaltkreises für den Standard 100Base-TX vorgestellt. Dieser PHY-Chip ermöglicht die Datenübertragung mit einer Datenrate von 100 MBit/s über verdrillte Kupferkabel und stellt darüber hinaus eine genaue Uhr bereit, welche zwischen den verbundenen Netzknoten synchronisiert werden kann. Dieser Schaltkreis ist insbesondere für Industrieanwendungen gedacht, bei denen verschiedene Prozesse zeitlich synchronisiert werden müssen. Prinzipiell ist der PHY-Chip jedoch universell für verschiedenste Anwendungen zur Zeitsynchronisation einsetzbar. Um die Genauigkeit der Zeitsynchronisation gegenüber herkömmlichen Ansätzen zu steigern, werden verschiedene Techniken untersucht und in dem entworfenen Schaltkreis eingesetzt. So wird die Phase der Taktsignale in feinen Schritten eingestellt und auch gemessen, sodass die Auflösung der Zeitstempel erheblich verbessert wird. Zu diesem Zweck wird ein sogenannter Digital-To-Phase Converter (DPC) eingesetzt, der 256 verschiedene Taktphasen des 125 MHz Systemtaktes bereitstellt. Für die eigentliche Zeitsynchronisation wird ein Proportional-Integral-Regler verwendet. Basierend auf einer theoretischen Rauschanalyse wird eine Methode vorgestellt, mit der die Parameter dieses Reglers so dimensioniert werden können, dass der Zeitfehler im eingeschwungenen Zustand möglichst klein wird. Darüber hinaus werden weitere Störeinflüsse analysiert und es werden geeignete Maßnahmen entwickelt, um diese zu kompensieren. So wird eine adaptive Kompensation eines Eintonstörers sowie eine Kalibrierung zur automatischen Kompensation von Asymmetrien im Kabel vorgestellt. All diese Punkte helfen, eine hervorragende Genauigkeit der Zeitsynchronisation zu ermöglichen, was durch umfangreiche Messungen verifiziert wird. Insgesamt weist der gemessene Zeitfehler in einem Punkt-zu-Punkt-Szenario eine Standardabweichung von 64 ps und einen Mittelwert unterhalb von 100 ps auf. Dies stellt eine erhebliche Verbesserung gegenüber konventionellen Lösungen zur Zeitsynchronisation über kupferbasiertes Ethernet dar, mit denen Genauigkeiten im Nanosekundenbereich erreicht werden. Als zweites Ziel dieser Arbeit wird der PHY-Chip für eine möglichst niedrige Leistungsaufnahme optimiert. Um dies zu erreichen, werden insbesondere der Leitungstreiber im Sender und der Equalizer im Empfänger systematisch optimiert. So werden zwei verschiedene Topologien von Leitungstreibern untersucht und verglichen. Beide weisen eine Leistungsaufnahme von etwa 24 mW auf. Im Vergleich zum Stand der Technik sind dies die beiden niedrigsten Werte für Leitungstreiber für den Standard 100Base-TX. Der gesamte PHY-Chip, der in einer 180 nm Technologie implementiert wurde, weist durch die zahlreichen Optimierungen eine geringe Leistungsaufnahme von maximal 69 mW auf, was ebenfalls einen Rekordwert im Vergleich mit dem Stand der Technik darstellt (80 mW). Die einzelnen Schaltungen wurden sowohl simulativ als auch mit ausführlichen Messungen verifiziert. Für den gesamten Link wird eine Bitfehlerrate besser als 10⁻¹² bei verschiedenen Kabeln bis zu 120 m Länge erreicht.:Abbildungsverzeichnis Tabellenverzeichnis Abkürzungen Symbole 1 Einleitung 1.1 Zeit und Zeitsynchronisation 1.2 Ziele dieser Arbeit 1.3 Gliederung 2 Grundlagen 2.1 100Base-TX Ethernet-Standard 2.1.1 Schnittstelle zur MAC-Schicht 2.1.2 4B5B-Kodierung 2.1.3 Scrambler und Descrambler 2.1.4 MLT-3-Kodierung 2.1.5 Bitfehlerrate und Signal-Rausch-Verhältnis 2.2 Kanalmodellierung 2.2.1 Dämpfung 2.2.2 Baseline-Wander 2.3 Zeitsynchronisierung 2.3.1 Bestimmung der Zeitdifferenz 2.3.2 Vergrößerung der Synchronisationsgenauigkeit 3 Schaltungsentwurf und Charakterisierung 3.1 Energieeffiziente Leitungstreiber 3.1.1 Vergleich von Leitungstreibern mit passiver Anpassung 3.1.2 Spannungstreiber 3.1.3 Leitungstreiber mit aktiver Anpassung 3.1.4 Vergleich der Leitungstreiber und Fazit 3.2 Takterzeugung 3.2.1 Ringoszillator 3.2.2 Phasenregelschleife 3.2.3 Phaseninterpolator 3.2.4 Messung 3.2.5 Verbesserter 10 Bit DPC 3.3 Takt- und Datenrückgewinnung 3.3.1 Phasendetektor 3.3.2 Modellierung des DPC 3.3.3 Dimensionierung des Schleifenfilters 3.3.4 Implementierung 3.4 Adaptiver Equalizer 3.4.1 Kompensation der Kabeldämpfung 3.4.2 Implementierung des analogen Filters 3.4.3 Digitale Regelung der Equalizer-Parameter 3.4.4 Messung des Equalizers 3.5 Zeitsynchronisation 3.5.1 Uhr und Steuerung der Frequenz 3.5.2 Digitale Schaltungen zur Zeitstempelung 3.5.3 Implementierung der Zeitsynchronisation 3.5.4 Adaptive Unterdrückung eines Eintonstörers 3.5.5 Automatische Kalibrierung von Asymmetrien 3.5.6 Vergleich mit dem Stand der Technik 3.6 Gesamter PHY-Schaltkreis 3.6.1 Leistungsaufnahme 3.6.2 Vergleich mit dem Stand der Technik 4 Zusammenfassung und Ausblick Literaturverzeichnis Eigene Veröffentlichungen / This work investigates accurate time synchronization over copper-based Ethernet systems as well as the design of circuits for the physical layer (PHY) in such Ethernet systems. The design of an integrated circuit (IC) for the 100Base-TX standard is presented. This PHY-IC enables data transmission at a data rate of 100 MBit/s over twisted pair copper cables and, additionally, provides an accurate clock which can be synchronized between connected network nodes. This circuit is designed for industrial applications where various processes need to be synchronized in time. In principle, however, the PHY-IC can be used universally for various time synchronization applications. In order to increase the accuracy of the time synchronization compared to conventional approaches, various techniques are investigated and used in the designed circuit. For example, the phase of the clock signals is adjusted and measured in fine steps, such that the resolution of the timestamps is improved by a large amount. For this purpose, a digital-to-phase converter (DPC) is used, which provides 256 different clock phases of the 125 MHz system clock. A proportional integral controller is used for the actual time synchronization application. Based on a theoretical noise analysis, a method is presented to dimension the parameters of this controller to minimize the timing error in the steady state. Furthermore, other disturbing influences are analyzed and suitable measures are developed to compensate them. Thus, an adaptive compensation of a single-tone interferer is presented as well as a calibration to automatically compensate for asymmetries in the cable. All these points help to provide excellent accuracy of the time synchronization, which is verified by extensive measurements. Overall, the measured time error in a point-to-point scenario has a standard deviation of 64 ps and a mean value below 100 ps. This represents a significant improvement over conventional solutions for time synchronization over copper-based Ethernet, which achieve accuracies in the nanosecond range. As a second goal of this work, the PHY-IC is optimized for lowest power consumption. In particular, the line driver in the transmitter and the equalizer in the receiver are systematically optimized to achieve this. Thus, two different topologies of line drivers are investigated and compared. Both have a power consumption of about 24 mW. These represent the two lowest values for line drivers for the 100Base-TX standard compared to the state of the art. The entire PHY-IC is implemented in a 180 nm technology and shows a power consumption below 69 mW due to the numerous optimizations. This also represents a record value compared to the state of the art (80 mW). The individual circuits were verified with simulations and with detailed measurements. For the entire link, a bit error rate better than 10⁻¹² is achieved for various cables up to 120 m length.:Abbildungsverzeichnis Tabellenverzeichnis Abkürzungen Symbole 1 Einleitung 1.1 Zeit und Zeitsynchronisation 1.2 Ziele dieser Arbeit 1.3 Gliederung 2 Grundlagen 2.1 100Base-TX Ethernet-Standard 2.1.1 Schnittstelle zur MAC-Schicht 2.1.2 4B5B-Kodierung 2.1.3 Scrambler und Descrambler 2.1.4 MLT-3-Kodierung 2.1.5 Bitfehlerrate und Signal-Rausch-Verhältnis 2.2 Kanalmodellierung 2.2.1 Dämpfung 2.2.2 Baseline-Wander 2.3 Zeitsynchronisierung 2.3.1 Bestimmung der Zeitdifferenz 2.3.2 Vergrößerung der Synchronisationsgenauigkeit 3 Schaltungsentwurf und Charakterisierung 3.1 Energieeffiziente Leitungstreiber 3.1.1 Vergleich von Leitungstreibern mit passiver Anpassung 3.1.2 Spannungstreiber 3.1.3 Leitungstreiber mit aktiver Anpassung 3.1.4 Vergleich der Leitungstreiber und Fazit 3.2 Takterzeugung 3.2.1 Ringoszillator 3.2.2 Phasenregelschleife 3.2.3 Phaseninterpolator 3.2.4 Messung 3.2.5 Verbesserter 10 Bit DPC 3.3 Takt- und Datenrückgewinnung 3.3.1 Phasendetektor 3.3.2 Modellierung des DPC 3.3.3 Dimensionierung des Schleifenfilters 3.3.4 Implementierung 3.4 Adaptiver Equalizer 3.4.1 Kompensation der Kabeldämpfung 3.4.2 Implementierung des analogen Filters 3.4.3 Digitale Regelung der Equalizer-Parameter 3.4.4 Messung des Equalizers 3.5 Zeitsynchronisation 3.5.1 Uhr und Steuerung der Frequenz 3.5.2 Digitale Schaltungen zur Zeitstempelung 3.5.3 Implementierung der Zeitsynchronisation 3.5.4 Adaptive Unterdrückung eines Eintonstörers 3.5.5 Automatische Kalibrierung von Asymmetrien 3.5.6 Vergleich mit dem Stand der Technik 3.6 Gesamter PHY-Schaltkreis 3.6.1 Leistungsaufnahme 3.6.2 Vergleich mit dem Stand der Technik 4 Zusammenfassung und Ausblick Literaturverzeichnis Eigene Veröffentlichungen
93

Uniting The Trinity of Ferroelectric HfO₂ Memory Devices in a Single Memory Cell

Slesazeck, Stefan, Havel, Viktor, Breyer, Evelyn, Mulaosmanovic, Halid, Hoffmann, Michael, Max, Benjamin, Duenkel, Stefan, Mikolajick, Thomas 21 February 2022 (has links)
The polarization reversal in ferroelectric HfO₂ is adopted to store information in three distinct device classes - ferroelectric field effect transistors (FeFET), ferroelectric capacitors (FeCAP) and ferroelectric tunnel junctions (FTJ). Common to all three concepts is the adoption of a ferroelectric layer stack that acts either as gate dielectric in the FeFET or as the capacitor dielectric and tunneling barrier in the FeCAP or FTJ, respectively. A composite structure including an inevitably or purposefully formed dielectric layer is frequently adopted. In this work we report on the co-existence of all three memory concepts within one device structure and propose a 2T1C ferroelectric memory cell that allows the operation and comparative characterization of the trinity of ferroelectric memory devices.
94

Computational Complexity and Delay Reduction for RLNC Single and Multi-hop Communications

Tasdemir, Elif 20 March 2023 (has links)
Today’s communication network is changing rapidly and radically. Demand for low latency, high reliability and low energy consumption increases as well the variety of characteristics of the connected devices. It is also expected that the number of connected devices will be massive in coming years. Some devices will be connected to the new generation base stations directly, while some of them will be connected through other devices via multi-hops. Reliable communication between these massive devices can be done via re-transmission, repetition of packets several times or via Forward Error Correction (FEC). In re-transmission method, when packets are negatively acknowledged or the sender’s acknowledgment timer expires, packets are re-transmitted. In repetition method, every packet can be send several times. Both aforementioned methods can cause a huge delay, particularly, in multi-hop network. On the contrary of these methods, FEC methods are preferred for low latency applications. Source information are transmitted together with redundant information. Hence, the number of transmissions are reduced comparing to the methods mentioned above. Random Linear Network Coding (RLNC) is a packet level erasure correcting codes which aims to reduce latency. Specifically, source packets are combined and these combinations or coded packets are sent to the destination. Lost packets do no need to be re-sent since another coded packet can be substituted to the lost coded packet. Hence, the feedback mechanism and re-sending process becomes unnecessary. There are many variations of RLNC. One variation is called sliding window RLNC which apples FEC mechanism. This coding scheme achieves low latency via interleaved coded packets in between source packets. Another variation of the RLNC is Fulcrum, which is a versatile code. Fulcrum provides three different decoding options. Received coded packets can be decoded with low, high or middle complexity. This is a very important feature since connected devices will have different computation capabilities and proving a versatile code will allow them flexibility. Although the aforementioned coding schemes are well suited to error prone network, there are still remaining challenges need to be studied. For instance, Fulcrum RLNC has high encoding and decoding complexity which increase the computation time and energy consumption. Moreover, although original Fulcrum RLNC strengths the reliability, it needs to be improved for low latency applications. Another remaining challenges is that recoding strategy of RLNC is not optimal for low latency. Allowing the intermediate nodes to combine received packets is referred as recoding. As described earlier, data packets will pass many hops until they reach destination. Therefore, compute-and-forward paradigm will be preferred rather than store-and-forward. Although recoding capability of RLNC differs it from other coding schemes (Raptor, LT), the conventional way of recoding is not efficient for low latency. Hence, the aim of this thesis is to address the aforementioned remaining challenges. One way to address the remaining challenges is to employ sparsity. In other words, a few source packets can be combined rather than a large set of source packets to generate coded packets. Particularly, a dynamic sparse mechanism is proposed to vary the number of combined source packets during the encoding without a signaling between sender and receiver for Fulcrum RLNC to speed up encoding and decoding process without increasing overhead amount. Then, two different sliding window schemes were integrated into Fulcrum RLNC to make Fulcrum RLNC gain the low latency property. Sending source packets systematically and then spreading sparse coded packets in between systematic source packets can be referred as systematic sparsity. Moreover, different sparse and systematic recoding strategies have been proposed in this thesis to lower the delay and computation time at the intermediate nodes and destination. Finally, one of the proposed recoding strategy has been applied to the vehicle platooning scenario to increase reliability. All proposed coding schemes were analyzed and performed on KODO which is well known network coding library.
95

Aktuelle Methoden der Background Subtraction und deren Anwendung als Vorverarbeitung einer Gestürzten-Personen-Erkennung

Brose, Jan 03 June 2022 (has links)
Das Thema dieser Arbeit ist die Entwicklung einer Background Subtraction und deren Verwendung in einer Gestürzten-Personen-Erkennung im Kontext eines Roboter Nachtwächters in einer Pflegeeinrichtung. Dazu wird der aktuelle technische Stand bei der Background Subtraction betrachtet. Im Anschluss daran wird basierend auf der Recherche und den Rahmenbedingungen die durch das Einsatzszenario gegeben sind ein Ansatz gewählt und umgesetzt. / The topic of this thesis is the development of a background subtraction and its use in a fallen person detection in the context of a robot night watchman in a care facility. For this purpose, the current technical status of background subtraction is considered. Subsequently, an approach is selected and implemented based on the research and the conditions given by the application scenario.
96

Studientexte zur Sprachkommunikation

Hoffmann, Rüdiger 01 September 2022 (has links)
No description available.
97

Surgical Instruments based on flexible micro-electronics

Rivkin, Boris 15 December 2022 (has links)
This dissertation explores strategies to create micro-scale tools with integrated electronic and mechanical functionalities. Recently developed approaches to control the shape of flexible micro-structures are employed to fabricate micro-electronic instruments that embed components for sensing and actuation, aiming to expand the toolkit of minimally invasive surgery. This thesis proposes two distinct types of devices that might expand the boundaries of modern surgical interventions and enable new bio-medical applications. First, an electronically integrated micro-catheter is developed. Electronic components for sensing and actuation are embedded into the catheter wall through an alternative fabrication paradigm that takes advantage of a self-rolling polymeric thin-film system. With a diameter of only 0.1 mm, the catheter is capable of delivering fluids in a highly targeted fashion, comprises actuated opposing digits for the efficient manipulation of microscopic objects, and a magnetic sensor for navigation. Employing a specially conceived approach for position tracking, navigation with a high resolution below 0.1 mm is achieved. The fundamental functionalities and mechanical properties of this instrument are evaluated in artificial model environments and ex vivo tissues. The second development explores reshapeable micro-electronic devices. These systems integrate conductive polymer actuators and strain or magnetic sensors to adjust their shape through feedback-driven closed loop control and mechanically interact with their environment. Due to their inherent flexibility and integrated sensory capabilities, these devices are well suited to interface with and manipulate sensitive biological tissues, as demonstrated with an ex vivo nerve bundle, and may facilitate new interventions in neural surgery.:List of Abbreviations 1 Introduction 1.1 Motivation 1.2 Objectives and structure of this dissertation 2 Background 2.1 Tools for minimally invasive surgery 2.1.1 Catheters 2.1.2 Tools for robotic micro-surgery 2.1.3 Flexible electronics for smart surgical tools 2.2 Platforms for shapeable electronics 2.2.1 Shapeable polymer composites 2.2.2 Shapeable electronics 2.2.3 Soft actuators and manipulators 2.3 Sensors for position and shape feedback 2.3.1 Magnetic sensors for position and orientation measurements 2.3.2 Strain gauge sensors 3 Materials and Methods 3.1 Materials for shapeable electronics 3.1.1 Metal-organic sacrificial layer 3.1.2 Polyimide as reinforcing material 3.1.3 Swelling hydrogel for self assembly 3.1.4 Polypyrrole for flexible micro actuators 3.2 Device fabrication techniques 3.2.1 Photolithography 3.2.2 Electron beam deposition 3.2.3 Sputter deposition 3.2.4 Atomic layer deposition 3.2.5 Electro-polymerization of polypyrrole 3.3 Device characterization techniques 3.3.1 Kerr magnetometry 3.3.2 Electro-magnetic characterization of sensors 3.3.3 Electro-chemical analysis of polypyrrole 3.3.4 Preparation of model environments and materials 3.4 Sensor signal evaluation and processing 3.4.1 Signal processing 3.4.2 Cross correlation for phase analysis 3.4.3 PID feedback control 4 Electronically Integrated Self Assembled Micro Catheters 4.1 Design and Fabrication 4.1.1 Fabrication and self assembly 4.1.2 Features and design considerations 4.1.3 Electronic and fluidic connections 4.2 Integrated features and functionalities 4.2.1 Fluidic transport 4.2.2 Bending stability 4.2.3 Actuated micro manipulator 4.3 Magnetic position tracking 4.3.1 Integrated magnetic sensor 4.3.2 Position control with sensor feedback 4.3.3 Introduction of magnetic phase encoded tracking 4.3.4 Experimental realization 4.3.5 Simultaneous magnetic and ultrasound tracking 4.3.6 Discussion, limitations, and perspectives 5 Reshapeable Micro Electronic Devices 5.1 Design and fabrication 5.1.1 Estimation of optimal fabrication parameters 5.1.2 Device Fabrication 5.1.3 Control electronics and software 5.2 Performance of Actuators 5.2.1 Blocking force, speed, and durability 5.2.2 Curvature 5.3 Orientation control with magnetic sensors 5.3.1 Magnetic sensors on actuated device 5.3.2 Reference magnetic field 5.3.3 Feedback control 5.4 Shape control with integrated strain sensors 5.4.1 Strain gauge curvature sensors 5.4.2 Feedback control 5.4.3 Obstacle detection 5.5 Heterogenous integration with active electronics 5.5.1 Fabrication and properties of active matrices 5.5.2 Fabrication and operation of PPy actuators 5.5.3 Site selective actuation 6 Discussion and Outlook 6.1 Integrated self assembled catheters 6.1.1 Outlook 6.2 Reshapeable micro electronic devices 6.2.1 Outlook 7 Conclusion Appendix A1 Processing parameters for polymer stack layers A2 Derivation of magnetic phase profile in 3D Bibliography List of Figures and Tables Acknowledgements Theses List of Publications
98

A Contribution to the Design of Highly Redundant Compliant Aerial Manipulation Systems

Yao, Chao 05 October 2022 (has links)
Es ist vorhersehbar, dass die Luftmanipulatoren in den nächsten Jahrzehnten für viele Aufgaben eingesetzt werden, die entweder zu gefährlich oder zu teuer sind, um sie mit herkömmlichen Methoden zu bewältigen. In dieser Arbeit wird eine neuartige Lösung für die Gesamtsteuerung von hochredundanten Luftmanipulationssystemen vorgestellt. Die Ergebnisse werden auf eine Referenzkonfiguration angewendet, die als universelle Plattform für die Durchführung verschiedener Luftmanipulationsaufgaben etabliert wird. Diese Plattform besteht aus einer omnidirektionalen Drohne und einem seriellen Manipulator. Um den modularen Regelungsentwurf zu gewährleisten, werden zwei rechnerisch effiziente Algorithmen untersucht, um den virtuellen Eingang den Aktuatorbefehlen zuzuordnen. Durch die Integration eines auf einem künstlichen neuronalen Netz basierenden Diagnosemoduls und der rekonfigurierbaren Steuerungszuordnung in den Regelkreis, wird die Fehlertoleranz für die Drohne erzielt. Außerdem wird die Motorsättigung durch Rekonfiguration der Geschwindigkeits- und Beschleunigungsprofile behandelt. Für die Beobachtung der externen Kräfte und Drehmomente werden zwei Filter vorgestellt. Dies ist notwendig, um ein nachgiebiges Verhalten des Endeffektors durch die achsenselektive Impedanzregelung zu erreichen. Unter Ausnutzung der Redundanz des vorgestellten Luftmanipulators wird ein Regler entworfen, der nicht nur die Referenz der Endeffektor-Bewegung verfolgt, sondern auch priorisierte sekundäre Aufgaben ausführt. Die Wirksamkeit der vorgestellten Lösungen wird durch umfangreiche Tests überprüft, und das vorgestellte Steuerungssystem wird als sehr vielseitig und effektiv bewertet.:1 Introduction 2 Fundamentals 3 System Design and Modeling 4 Reconfigurable Control Allocation 5 Fault Diagnostics For Free Flight 6 Force and Torque Observer 7 Trajectory Generation 8 Hybrid Task Priority Control 9 System Integration and Performance Evaluation 10 Conclusion / In the following decades, aerial manipulators are expected to be deployed in scenarios that are either too dangerous for human beings or too expensive to be accomplished by traditional methods. This thesis presents a novel solution for the overall control of highly redundant aerial manipulation systems. The results are applied to a reference configuration established as a universal platform for performing various aerial manipulation tasks. The platform consists of an omnidirectional multirotor UAV and a serial manipulator. To ensure modular control design, two computationally efficient algorithms are studied to allocate the virtual input to actuator commands. Fault tolerance of the aerial vehicle is achieved by integrating a diagnostic module based on an artificial neural network and the reconfigurable control allocation into the control loop. Besides, the risk of input saturation of individual rotors is minimized by predicting and reconfiguring the speed and acceleration responses. Two filter-based observers are presented to provide the knowledge of external forces and torques, which is necessary to achieve compliant behavior of the end-effector through an axis-selective impedance control in the outer loop. Exploiting the redundancy of the proposed aerial manipulator, the author has designed a control law to achieve the desired end-effector motion and execute secondary tasks in order of priority. The effectiveness of the proposed designs is verified with extensive tests generated by following Monte Carlo method, and the presented control scheme is proved to be versatile and effective.:1 Introduction 2 Fundamentals 3 System Design and Modeling 4 Reconfigurable Control Allocation 5 Fault Diagnostics For Free Flight 6 Force and Torque Observer 7 Trajectory Generation 8 Hybrid Task Priority Control 9 System Integration and Performance Evaluation 10 Conclusion
99

Fabrication and Characterization of AlGaN/GaN Metal-Insulator-Semiconductor High Electron Mobility Transistors for High Power Applications

Calzolaro, Anthony 11 October 2022 (has links)
AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) are promising candidates for next generation high-efficiency and high-voltage power applications. The excellent physical properties of GaN-based materials, featuring high critical electric field and large carrier saturation velocity, combined to the high carrier density and large mobility of the two-dimensional electron gas confined at the AlGaN/GaN interface, enable higher power density minimizing power losses and self-heating of the device. However, the advent of the GaN-based MIS-HEMT to the industrial production is still hindered by technological challenges that are being faced in parallel. Among them, one of the biggest challenge is represented by the insertion of a gate dielectric in MIS-HEMTs compared to Schottky-gate HEMTs, which causes operational instability due to the presence of high-density trap states located at the dielectric/III-nitride interface or within the dielectric. The development of a gold-free ohmic contact technology is another important concern since the high-volume and cost-effective production of GaN-based transistors also depends on the cooperative manufacturing of GaN-based devices in Si production facilities, where gold represents an undesidered source of contamination. In fact, even though over the past years there have been multiple attemps to develop gold-free ohmic contacts, there is still no full understanding of the contact formation and current transport mechanism. The first objective of this work was the investigation of a gold-free and low-resistive ohmic contact technology to AlGaN/GaN based on sputtered Ta/Al-based metal stacks annealed at low temperatures. A low contact resistance below 1 Ω mm was obtained using Ta/Al-based metal stacks annealed at temperatures below 600 °C. The ohmic behavior and the contact properties of contact resistance, optimum annealing temperature and thermal stability of Ta/Al-based contacts were studied. The nature of the current transport was also investigated indicating a contact mechanism governed by thermionic field emission tunneling through the AlGaN barrier. Finally, gold-free Ta/Al-based ohmic contacts were integrated in MIS-HEMTs fabricated on a 150 mm GaN-on- Si substrate, demonstrating to be a promising contact technology for AlGaN/GaN devices and revealing to be beneficial for devices operating at high temperatures. The optimization of the MIS-gate structure in terms of trap states at the dielectric/III-nitride interface and inside the dielectric in MIS-HEMTs using atomic layer deposited (ALD) Al2O3 as gate insulator was the second focus of this work. First, the MIS-gate structure was improved by an O2 plasma surface preconditioning applied before the Al2O3 deposition and by an N2 postmetallization anneal applied after gate metallization, which significantly reduced trap states at the Al2O3/GaN interface and within the dielectric. Afterwards, the effectiveness of these treatments was demonstrated in Al2O3-AlGaN/GaN MIS-HEMTs by pulsed current–voltage measurements revealing improved threshold voltage stability. Lastly, it was shown that also the lower annealing temperatures used for the formation of Ta/Al-based ohmic contacts, processed before gate dielectric deposition, are beneficial in terms of trap states at the ALD-Al2O3/GaN interface, representing a new aspect to be considered when using an ohmic first fabrication approach.
100

Optimization of niobium oxide-based threshold switches for oscillator-based applications

Herzig, Melanie 11 December 2023 (has links)
In niobium oxide-based capacitors non-linear switching characteristics can be observed if the oxide properties are adjusted accordingly. Such non-linear threshold switching characteristics can be utilized in various non-linear circuit applications, which have the potential to pave the way for the application of new computing paradigms. Furthermore, the non-linearity also makes them an interesting candidate for the application as selector devices e.g. for non-volatile memory devices. To satisfy the requirements for those two areas of application, the threshold switching characteristics need to be adjusted to either obtain a maximized voltage extension of the negative differential resistance region in the quasi-static I-V characteristics, which enhances the non-linearity of the devices and results in improved robustness to device-to-device variability or to adapt the threshold voltage to a specific non-volatile memory cell. Those adaptations of the threshold switching characteristics were successfully achieved by deliberate modifications of the niobium oxide stack. Furthermore, the impact of the material stack on the dynamic behavior of the threshold switches in non-linear circuits as well as the impact of the electroforming routine on the threshold switching characteristics were analyzed. The optimized device stack was transferred from the micrometer-sized test structures to submicrometer-sized devices, which were packaged to enable easy integration in complex circuits. Based on those packaged threshold switching devices the behavior of single as well as of coupled relaxation oscillators was analyzed. Subsequently, the obtained results in combination with the measurement results for the statistic device-to-device variability were used as a basis to simulate the pattern formation in coupled relaxation oscillator networks as well as their performance in solving graph coloring problems. Furthermore, strategies to adapt the threshold voltage to the switching characteristics of a tantalum oxide-based non-volatile resistive switch and a non-volatile phase change cell, to enable their application as selector devices for the respective cells, were discussed.:Abstract I Zusammenfassung II List of Abbrevations VI List of Symbols VII 1 Motivation 1 2 Basics 5 2.1 Negative differential resistance and local activity in memristor devices 5 2.2 Threshold switches as selector devices 8 2.3 Switching effects observed in NbOx 13 2.3.1 Threshold switching caused by metal-insulator transition 13 2.3.2 Threshold switching caused by Frenkel-Poole conduction 18 2.3.3 Non-volatile resistive switching 32 3 Sample preparation 35 3.1 Deposition techniques 35 3.1.1 Evaporation 35 3.1.2 Sputtering 36 3.2 Micrometer-sized devices 36 3.3 Submicrometer-sized devices 37 3.3.1 Process flow 37 3.3.2 Reduction of the electrode resistance 39 3.3.3 Transfer from structuring via electron beam lithography to structuring via laser lithography 48 3.3.4 Packaging procedure 50 4 Investigation and optimization of the electrical device characteristic 51 4.1 Introduction 51 4.2 Measurement setup 52 4.3 Electroforming 53 4.3.1 Optimization of the electroforming process 53 4.3.2 Characterization of the formed filament 62 4.4 Dynamic device characteristics 67 4.4.1 Emergence and measurement of dynamic behavior 67 4.4.2 Impact of the dynamic device characteristics on quasi-static I-V characteristics 70 5 Optimization of the material stack 81 5.1 Introduction 81 5.2 Adjustment of the oxygen content in the bottom layer 82 5.3 Influence of the thickness of the oxygen-rich niobium oxide layer 92 5.4 Multilayer stacks 96 5.5 Device-to-device and Sample-to-sample variability 110 6 Applications of NbOx-based threshold switching devices 117 6.1 Introduction 117 6.2 Non-linear circuits 117 6.2.1 Coupled relaxation oscillators 117 6.2.2 Memristor Cellular Neural Network 121 6.2.3 Graph Coloring 127 6.3 Selector devices 132 7 Summary and Outlook 138 8 References 141 9 List of publications 154 10 Appendix 155 10.1 Parameter used for the LT Spice simulation of I-V curves for threshold switches with varying oxide thicknesses 155 10.2 Dependence of the oscillation frequency of the relaxation oscillator circuit on the capacitance and the applied source voltage 156 10.3 Calculation of the oscillation frequency of the relaxation oscillator circuit 157 10.4 Characteristics of the memristors and the cells utilized in the simulation of the memristor cellular neural network 164 10.5 Calculation of the impedance of the cell in the memristor cellular network 166 10.6 Example graphs from the 2nd DIMACS series 179 11 List of Figures 182 12 List of Tables 194

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