<p>Beroende på i vilken miljö man har tänkt att använda trådlös kommunikation behöver man hitta en modulationsteknik som passar under rådande förhållanden. I början på 1980-talet utvecklade den Amerikanska militären en modulationsteknik som kallas för Shaped BPSK (SBPSK) avsedd att tillämpas i kommunikationslänkar med satelliter. Vidareutveckling av SBPSK ledde sedan fram till en förbättrad variant kallad Shaped Offset QPSK (SOQPSK). På senare år har denna modulationsteknik börjat användas i civila tillämpningar och vidareutvecklats ytterligare för att ge den än bättre prestanda. År 2004 antogs SOQPSK som en modulationsteknik i den internationella flygplanskommunikationsstandarden, IRIG-106. Versionen av SOQPSK som antogs i IRIG-106 har flera bra egenskaper som t. ex. dess spektraltäthet. Detta gör denna typ av modulationsteknik lämpad för kommunikationslänkar med bl.a. flygplan, satelliter och rymdsonder (‘deep-space’).</p><p>Målet med examensarbetet har varit att implementera algoritmer för att skicka och ta emot SOQPSK-modulerade signaler. Dessa algoritmer skulle utvecklas i VHDL för att sedan syntetiseras och programmera en FPGA. Uppgiften har givits av Syncore Technologies AB i Linköping.</p><p>Arbetet har resulterat i fungerande implementationer både i mjukvara och hårdvara. Hårdvarulösningen är verifierad att klara bithastiheter upp till 30 Mbit/s. Teoretisk information om allmän modulering/demodulering och specifikt kring SOQPSK behandlas i rapporten. Uppbyggnaden av en teoretisk sändar- och mottagarmodell utformad för SOQPSK-kommunikation beskrivs också i rapporten för att ge en bättre helhetsbild av implementationen som utförts.</p><p>Arbetets syfte är att ligga till grund för Syncore AB som utvecklar en kom- munikationslänk med SOQPSK-kompatibilitet.</p>

Beroende på i vilken miljö man har tänkt att använda trådlös kommunikation behöver man hitta en modulationsteknik som passar under rådande förhållanden. I början på 1980-talet utvecklade den Amerikanska militären en modulationsteknik som kallas för Shaped BPSK (SBPSK) avsedd att tillämpas i kommunikationslänkar med satelliter. Vidareutveckling av SBPSK ledde sedan fram till en förbättrad variant kallad Shaped Offset QPSK (SOQPSK). På senare år har denna modulationsteknik börjat användas i civila tillämpningar och vidareutvecklats ytterligare för att ge den än bättre prestanda. År 2004 antogs SOQPSK som en modulationsteknik i den internationella flygplanskommunikationsstandarden, IRIG-106. Versionen av SOQPSK som antogs i IRIG-106 har flera bra egenskaper som t. ex. dess spektraltäthet. Detta gör denna typ av modulationsteknik lämpad för kommunikationslänkar med bl.a. flygplan, satelliter och rymdsonder (‘deep-space’). Målet med examensarbetet har varit att implementera algoritmer för att skicka och ta emot SOQPSK-modulerade signaler. Dessa algoritmer skulle utvecklas i VHDL för att sedan syntetiseras och programmera en FPGA. Uppgiften har givits av Syncore Technologies AB i Linköping. Arbetet har resulterat i fungerande implementationer både i mjukvara och hårdvara. Hårdvarulösningen är verifierad att klara bithastiheter upp till 30 Mbit/s. Teoretisk information om allmän modulering/demodulering och specifikt kring SOQPSK behandlas i rapporten. Uppbyggnaden av en teoretisk sändar- och mottagarmodell utformad för SOQPSK-kommunikation beskrivs också i rapporten för att ge en bättre helhetsbild av implementationen som utförts. Arbetets syfte är att ligga till grund för Syncore AB som utvecklar en kom- munikationslänk med SOQPSK-kompatibilitet.

The objective of this research is to present a low power modem technology for a high speed millimeter wave wireless system. The first part of the research focuses on a robust ASIC design methodology. There are several aspects of the ASIC flow that require special attention such as logical synthesis, timing driven physical placement, Clock Tree Synthesis, Static Timing Analysis, estimation and reduction of power consumption and LVS and DRC closure. The latter part is dedicated to high speed baseband circuits such as Coherent and Non coherent demodulator which are critical components of a multi-gigabit wireless communication system. The demodulator operates at input data rates of multiple gigabits per second, which presents the challenge of designing the building blocks to operate at speeds of multiple GHz. The high speed complex multiplier is a major component of the non coherent demodulator. As part of the coherent demodulator the complex multiplier derotates the input sequence by multiplying with cosine and sine functions, Costas error calculator computes the phase error in the derotated input signal. The NCO (Numerically controlled Oscillator) is a look up table based system used to generate the cosine and sine functions, used by the derotator.The CIC filter is used to decimate the costas error signal as the loop bandwidth is significantly smaller compared to the sampling frequency. All these modules put together form the coherent demodulator which is an integral part of the wireless communication system. An implementation of Serdes is also presented which acts as an interface between the baseband modules and the RF front end.

International Telemetering Conference Proceedings / October 17-20, 1994 / Town & Country Hotel and Conference Center, San Diego, California / This paper analyzes the probability of bit error for PCM-FM over a standard IRIG channel subject to multipath interference modeled by the aeronautical fading channel. The aeronautical channel model assumes a mobile transmitter and a stationary receiver and specifies the correlation of the fading component. This model describes fading which is typical of that encountered at military test ranges. An expression for the bit error rate on the fading channel with a delay line demodulator is derived and compared with the error rate for the Gaussian channel. The increase in bit error rate over that of the Gaussian channel is determined along with the power penalty caused by the fading. In addition, the effects of several channel parameters on the probability of bit error are determined.

This thesis includes two topics, which are a Self-sampled ALL-MOS ASK Demodulator and a Synchronous DAC with Self-calibration. An all-MOS ASK demodulator with a wide bandwidth for lower ISM band applications is presented in the first half of this thesis. The chip area is reduced without using any passive element. It is very compact to be integrated in an SOC (system-on-chip) for wireless biomedical applications, particularly in biomedical implants. Because of low area cost and low power consumption, the proposed design is also easily to be integrated in other mobile medical devices. The self-sampled loop with a MOS equivalent capacitor compensation mechanism enlarges the bandwidth, which is more than enough to be adopted in any application using lower ISM bands. To demonstrate this technique, an ASK demodulator prototype is implemented and measured using a TSMC 0.35 £gm standard CMOS process. The second topic reveals a synchronous DAC with self-calibration. The main idea is to use a calibration circuit to overcome large error of output voltage caused by the variation of the unit capacitor. When DAC is not calibrated, INL is larger than 1.7 LSB. After calibrated, INL is improved to be smaller than 0.5 LSB. To demonstrate this technique, a DAC prototype is implemented and measured using a TSMC 0.18 £gm standard CMOS process.

This research investigates robust demodulation of Gaussian Minimum Shift Keying (GMSK) signals, using demodulator diversity and real-time bit-error-rate (BER) estimation. GMSK is particularly important because of its use in promi- nent wireless standards around the world (GSM, DECT, CDPD, DCS1800, and PCS1900). The dissertation begins with a literature review of GMSK demodu- lation techniques (coherent and noncoherent) and includes an overview of single- channel interference rejection techniques in digital wireless communications. Vari- ous forms of GMSK demodulation are simulated, including the limiter discrimina- tor and di erential demodulator (i.e., twenty-five variations in all). Ten represent new structures and variations. The demodulator performances are evaluated in realistic wireless environments, such as additive white Gaussian noise, co-channel interference, and multipath environments modeled by COST207 and SMRCIM. Certain demodulators are superior to others for particular channel impairments, so that no demodulator is necessarily the best in every channel impairment. This research formally introduces the concept of demodulator diversity, a new idea which consists of a bank of demodulators which simultaneously demodulate the same signal and take advantage of the redundancy in the similar signals. The dissertation also proposes practical real-time BER estimation techniques which have tremendous ramifications for communications. Using Parzen's estimator for probability density functions (pdfs) and Gram-Charlier series approximation for pdfs, BER can be estimated using short observation intervals (10 to 500 training symbols) and, in some cases, without any training sequence. We also introduce new variations of Gram-Charlier estimation using robust estimators. BER (in place of MSE) can now drive adaptive signal processing. Using a cost function and gradient for Parzen's estimator (derived in this paper), BER estimation is applied to demodulator diversity with substantial gains of 1-10 dB in carrier- to-interference ratio over individual receivers in realistic channels (with adaptive selection and weighting). With such gains, a BER-based demodulator diversity scheme can allow the employment of a frequency reuse factor of N = 4, instead of N = 7, with no degradation in performance. A lower reuse factor means more channels are available in a cell, thus increasing overall capacity. The resulting techniques are simple and easily implemented at the mobile. BER estimation techniques can also be used in BER-based equalization and dynamic allocation of resources. / Ph. D.

International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, Nevada / Eglin Air Force Base (AFB) plans to demonstrate subminiature telemetry (SMT) spread spectrum technology, via an upgraded prototype SMT system, to validate its cost-effectiveness for both Department of Defense (DoD) and commercial use. The goal is to develop new and/or modify current SMT instrumentation using existing production methods to provide increased capabilities at lower costs and reduced size. The transmitter is to require less than 2 cubic inches of space and have a cost goal of $500/unit "in quantity." The cost goal of a ground-based, 24-channel capable ground receiver is $4000/unit "in quantity". The SMT project as well as its schedule, flight and ground demonstrations, validation criteria and goals, and various benefits are discussed.

The thesis is composed of two topics: A SOC design for one-time implantable spinal cord stimulation system ¡]SCS¡^, and the design of an inter-chip capacitance coupling circuit. In the first topic, the SOC design using wireless power and data transmission techniques for the SCS system is presented in this work. The proposed SOC can control 4 electrodes to generate different patterns of stimulation waves. It has multiple modes to drive whole the SCS system. Notably, the SOC contains a novel ASK demodulator which converts the ASK signals into digital signals reliably. The SOC is implemented using a typical 0.18-£gm 1P6M CMOS process. The chip area is only 1.71 * 1.41 mm2. Besides, the volume of the implantable SCS pulse generator utilizing this SOC is less than 24 cm3, and the power consumption is only 59.4 mW. In the second topic, a high-speed inter-chip capacitance coupling circuit is presented. Digital signals between two chips can be transceived through capacitive coupling of the proposed circuit. Notably, the transceivers are designed below the capacitors to attain the area reduction. It is an advanced application for high-speed wafer testing and 3D IC communication. A prototype chip is presented to achieve 2 Gbps on silicon using a typical 0.18 £gm 1P6M CMOS process. The chip area is 1045 ¡Ñ 894 £gm2. Besides, it only costs 21.47 mW in terms of power consumption. This capacitive coupling technique for high-speed digital circuit has great potential in the coming future.

This thesis includes two topics. The first one is a low-power double-edge triggered flip-flop.The other is a orthogonal frequency division multiplex (OFDM) demodulator compliant with the Digital Video Broadcasting Handheld (DVB-H). Low-power double-edge triggered flip-flop (DETFF) is based on multi-Vth transistors technique. Since low threshold voltage transistors are able to generate large leakage current, they are suitable to drive big loads. By contrast, high threshold voltage transistors are more appropriate to latch data due to their low leakage. Therefore, a single latch double-edge triggered flip-flop utilizing multi-Vth transistors can be a low power and high speed design without paying the price of large area. The proposed OFDM demodulator is compliant with the DVB-H standard. The received DVB-H signal is processed by an RF front-end and the following analog-to-digital converter. Then, the digital signal is fed into the demodulator to adjust and calibrate the frequency, timing offset and channel estimation. The proposed DVB-H demodulator is mainly composed of five blocks : symbol timing synchronization block, carrier frequency offset compensation block, fast Fourier transform block, scatter pilot detection block and channel compensation block.

Increased challenges in CMOS scaling have motivated the development of alternatives to silicon circuit technologies, including graphene transistor development. In this work, we present a circuit simulator model for graphene FETs, developed to both fit measured data and predict new behaviors, motivating future research. The model is implemented in Agilent ADS, a circuit level simulator that is commonly used for non-standard transistor technologies, for use with parameter variation analyses, as well as easy integration with CMOS design kits. We present conclusions drawn from the model, including analyses on the effects of contact resistance and oxide scaling. We have also derived a quantum-capacitance limited model, used to intuit intrinsic behaviors of graphene transistors, as well as outline upper bounds on performance. Additionally, the ideal frequency doubler has been examined and compared with graphene, and performance limits for graphene frequency multipliers are elucidated. Performance as a demodulator is also discussed. We leverage this advancement in modeling research to advance circuit- and system-level research using graphene transistor technology. We first explore the development of a GHz planar carbon antenna for use on an RF frontend. This research is further developed in work towards the first standalone carbon radio on flexible plastics. A front end receiver, comprised of an integrated carbon antenna, transmission lines, and a graphene transistor for demodulation, are all fabricated onto one plastic substrate, to be interfaced with speakers for a full radio demo. This complete system will motivate further research on graphene-on-plastic systems. / text