O presente trabalho faz inicialmente uma revisão básica a respeito de diodos controlados por porta ressaltando o método criado por Grove, e corrigido por Pierret, para a determinação da velocidade de recombinação superficial, parâmetro esse, importante na análise do desempenho do dispositivo frente a situações que tendem a degradar o funcionamento do mesmo. Em seguida, propomos a utilização de DCP\'s como sensores de radiação luminosa e possivelmente como sensor de cores. Para tanto, simulamos o comportamento de uma junção PN sob iluminação quando variamos a extensão da região de depleção associada à mesma. De acordo com essas simulações, observamos que o rendimento de conversão da energia luminosa para elétrica, em função do comprimento de onda da luz incidente, apresenta dependência com relação a extensão da região de carga espacial. Essa característica pode vir a ser usada, futuramente, na detecção seletiva de comprimentos de onda, e portanto, permitindo a discriminação de cores. A variação da largura da região de depleção nas proximidades de uma junção PN pode ser conseguida, numa estrutura do tipo DCP, através da aplicação em sua porta, de pulsos de amplitude e inclinação adequadas, de forma a levá-lo a operar em depleção profunda. Nessas condições, o valor máximo da largura da região de depleção é maior do que o seu valor máximo estacionário, podendo chegar a até 3 vezes o mesmo, conforme foi constatado por simulação, através de um software por nós desenvolvido, para uma estrutura MOS pulsada. Tal simulação forneceu-nos o campo e potencial elétricos e a concentração de portadores em função da profundidade através da resolução da equação de Poisson com condições de contorno adequadas. Dados os resultados obtidos nas simulações, a próxima etapa foi a elaboração de máscaras litográficas para construir diodos controlados por porta com diferentes geometrias, algumas sugeridas pela literatura, outras ) desenvolvidas para esse trabalho. Tais máscaras foram confeccionadas pelo CTI em Campinas e foram desenhadas através do software Microeletrônica de Etienne Sicard da universidade de Toulouse. Utilizamos as máscaras fabricadas para construir uma pastilha-teste preliminar com os diodos controlados por porta propostos. Infelizmente, nesta única corrida, tivemos curto-circuito entre porta e substrato e apenas as junções PN funcionaram a contento. Obtivemos diodos com fator de idealidade de ~1,4 e densidade de corrente reversa, no melhor dos casos, igual a 1,23.104 nA/cm² para áreas de (1000 x 1000) µm². Por outro lado, como não conseguimos DCP\'s funcionando, utilizamos transistores nMOS convencionais, fornecidos pelo Prof. João Antonio Martino, para medir a velocidade de recombinação superficial, \"velocidade de recombinação aparente\", que resultou em 5,5×106 cm/s, segundo o método proposto por Pierret. / This work presents a basic review about gate-controlled diodes (GCD) mainly on the method created by Grove and corrected by Pierret, for measuring the surface recombination velocity that is an important parameter on the analysis of device performance. In the sequence, we propose the use of GCD\'s as light radiation sensors and, probably as color sensors. To do so, we have simulated the behavior of a PN junction under illumination, varying the depletion region length. The simulations revealed that the luminous to electrical energy conversion depends on the length of the spatial charge region. This could be used, in the future, on the selective wavelength detection, alloying color discrimination. The variation of the depletion region length in the vicinity of a PN junction can be done, in a GCD structure, by applying in its gate, a set of electrical pulses with the right characteristics, in order to drive it to the deep depletion mode. In these conditions, the maximum length of the depletion region is larger than its steady state value, reaching as much as 3 times that value, as could be determined by means of simulation of a pulsed MOS structure, in a specific software developed for that purpose. This software give us the electric field and potencial and the carrier concentration against depth into the silicon by solving the Poisson equation with the right boundary conditions. Keeping these results in mind, the next step was the project of the lithographic masks in order to explore some different geometries, some of them suggested by the literature, others developed in this work. The fabrication of those masks were done by CTI in Campinas e were designed with the software Microeletrônica by Etienne Sicard from the university of Toulouse. We have used the masks to manufacture a preliminary chip test which included gate-controled diodes.Unfortunately, in this unique run, \"short circuits\" between gate and bulk has occurred and only the PN junctions worked as expected. We have obtained diodes with ideality factor of ~1.4 and reverse current density of 1.23.104 nA/cm² in the best case for junction areas of (1000 x 1000) µm². On the other hand, as we have not got gate-controlled diodes which were working, we have used conventional nMOS transistors borrowed by Prof. João Antônio Martino. Surface recombination velocity so was measured in these nMOS transistors and resulted in 5.5.106 cm/s, according to the method proposed by Pierret.

abstract: GaAs-based solar cells have attracted much interest because of their high conversion efficiencies of ~28% under one sun illumination. The main carrier recombination mechanisms in the GaAs-based solar cells are surface recombination, radiative recombination and non-radiative recombination. Photon recycling reduces the effect of radiative recombination and is an approach to obtain the device performance described by detailed balance theory. The photon recycling model has been developed and was applied to investigate the loss mechanisms in the state-of-the-art GaAs-based solar cell structures using PC1D software. A standard fabrication process of the GaAs-based solar cells is as follows: wafer preparation, individual cell isolation by mesa, n- and p-type metallization, rapid thermal annealing (RTA), cap layer etching, and anti-reflection coating (ARC). The growth rate for GaAs-based materials is one of critical factors to determine the cost for the growth of GaAs-based solar cells. The cost for fabricating GaAs-based solar cells can be reduced if the growth rate is increased without degrading the crystalline quality. The solar cell wafers grown at different growth rates of 14 μm/hour and 55 μm/hour were discussed in this work. The structural properties of the wafers were characterized by X-ray diffraction (XRD) to identify the crystalline quality, and then the as-grown wafers were fabricated into solar cell devices under the same process conditions. The optical and electrical properties such as surface reflection, external quantum efficiency (EQE), dark I-V, Suns-Voc, and illuminated I-V under one sun using a solar simulator were measured to compare the performances of the solar cells with different growth rates. Some simulations in PC1D have been demonstrated to investigate the reasons of the different device performances between fast growth and slow growth structures. A further analysis of the minority carrier lifetime is needed to investigate into the difference in device performances. / Dissertation/Thesis / M.S. Electrical Engineering 2014

The trichromatic principle of representing color has for a long time been dominating in color imaging. The reason is the trichromatic nature of human color vision, but as the characteristics of typical color imaging devices are different from those of human eyes, there is a need to go beyond the trichromatic approach. The interest for multi-channel imaging, i.e. increasing the number of color channels, has made it an active research topic with a substantial potential of application. To achieve consistent color imaging, one needs to map the imaging-device data to the device-independent colorimetric representations CIEXYZ or CIELAB, the key concept of color management. As the color coordinates depend not only on the reflective spectrum of the object but also on the spectral properties of the illuminant, the colorimetric representation suffers from metamerism, i.e. objects of the same color under a specific illumination may appear different when they are illuminated by other light sources. Furthermore, when the sensitivities of the imaging device differ from the CIE color matching functions, two spectra that appear different for human observers may result in identical device response. On contrary, in multispectral imaging, color is represented by the object’s physical characteristics namely the spectrum which is illuminant independent. With multispectral imaging, different spectra are readily distinguishable, no matter they are metameric or not. The spectrum can then be transformed to any color space and be rendered under any illumination. The focus of the thesis is high quality image-acquisition in colorimetric and multispectral formats. The image acquisition system used is an experimental system with great flexibility in illumination and image acquisition setup. Besides the conventional trichromatic RGB filters, the system also provides the possibility of acquiring multi-channel images, using 7 narrowband filters. A thorough calibration and characterization of all the components involved in the image acquisition system is carried out. The spectral sensitivity of the CCD camera, which can not be derived by direct measurements, is estimated using least squares regression, optimizing the camera response to measured spectral reflectance of carefully selected color samples. To derive mappings to colorimetric and multispectral representations, two conceptually different approaches are used. In the model-based approach, the physical model describing the image acquisition process is inverted, to reconstruct spectral reflectance from the recorded device response. In the empirical approach, the characteristics of the individual components are ignored, and the functions are derived by relating the device response for a set of test colors to the corresponding colorimetric and spectral measurements, using linear and polynomial least squares regression. The results indicate that for trichromatic imaging, accurate colorimetric mappings can be derived by the empirical approach, using polynomial regression to CIEXYZ and CIELAB. Because of the media-dependency, the characterization functions should be derived for each combination of media and colorants. However, accurate spectral data reconstruction requires for multi-channel imaging, using the model-based approach. Moreover, the model-based approach is general, since it is based on the spectral characteristics of the image acquisition system, rather than the characteristics of a set of color samples. / Report code: LiU-TEK-LIC- 2006:70

The trend of electrification in transportation applications has led to the fast development of high-power-density power electronics converters. High-switching-frequency and high-temperature operations are the two key factors towards this target. Both requirements, however, are challenging the fundamental limit of silicon (Si) based devices. The emerging wide-bandgap, silicon carbide (SiC) power devices have become the promising solution to meet these requirements. With these advanced devices, the technology barrier has now moved to the compatible integration technology that can make the best of device capabilities in high-power-density converters. Many challenges are present, and some of the most important issues are explored in this dissertation. First of all, the high-temperature performances of the commercial SiC MOSFET are evaluated extensively up to 200 degree C. The static and switching characterizations show that the device has superior electrical performances under elevated temperatures. Meanwhile, the gate oxide stability of the device - a known issue to SiC MOSFETs in general - is also evaluated through both high-temperature gate biasing and gate switching tests. Device degradations are observed from these tests, and a design trade-off between the performance and reliability of the SiC MOSFET is concluded. To understand the interactions between devices and circuit parasitics, an experimental parametric study is performed to investigate the influences of stray inductances on the MOSFETs switching waveforms. A small-signal model is then developed to explain the parasitic ringing in the frequency domain. From this angle, the ringing mechanism can be understood more easily and deeply. With the use of this model, the effects of DC decoupling capacitors in suppressing the ringing can be further explained in a more straightforward way than the traditional time-domain analysis. A rule of thumb regarding the capacitance selection is also derived. A Power Electronics Building Block (PEBB) module is then developed with discrete SiC MOSFETs. Integrating the power stage together with the peripheral functions such as gate drive and protection, the PEBB concept allows the converter to be built quickly and reliably by simply connecting several PEBB modules. The high-speed gate drive and power stage layout designs are presented to enable fast and safe switching of the SiC MOSFET. Based on the PEBB platform, the state-of-the-art Si and SiC power MOSFETs are also compared in the device characteristics, temperature influences, and loss distributions in a high-frequency converter, so that special design considerations can be concluded for the SiC MOSFET. Towards high-temperature, high-frequency and high-power operations, integrated wire-bond phase-leg modules are also developed with SiC MOSFET bare dice. High-temperature packaging materials are carefully selected based on an extensive literature survey. The design considerations of improved substrate layout, laminated bus bars, and embedded decoupling capacitors are all discussed in detail, and are verified through a modeling and simulation approach in the design stage. The 200 degree C, 100 kHz continuous operation is demonstrated on the fabricated module. Through the comparison with a commercial SiC phase-leg module designed in the traditional way, it is also shown that the design considerations proposed in this work allow the SiC devices in the wire-bond structure to be switched twice as fast with only one-third of the parasitic ringing. To further push the performance of SiC power modules, a novel hybrid packaging technology is developed which combines the small parasitics and footprint of a planar module with the easy fabrication of a wire-bond module. The original concept is demonstrated on a high-temperature rectifier module with SiC JFET. A modified structure is then proposed to further improve design flexibility and simplify module fabrication. The SiC MOSFET phase-leg module built in this structure successfully reaches the switching speed limit of the device almost without any parasitic ringing. Finally, a new switching loop snubber circuit is proposed to damp the parasitic ringing through magnetic coupling without affecting either conduction or switching losses of the device. The concept is analyzed theoretically and verified experimentally. The initial integration of such a circuit into the power module is presented, and possible improvements are proposed. / Ph. D.

Reducing supply voltage is a promising way to address the power dissipation in nano-electronic circuits. However, the fundamental lower limit of subthreshold slope (SS) within metal-oxide-semiconductor field-effect transistors (MOSFETs) is a major obstacle to further scaling the operation voltage without degrading ON/OFF-ratio in today's integrated circuits. Tunnel field-effect transistors (TFETs) benefit from steep switching characteristics due to the quantum-mechanical tunneling injection of carriers from source to channel, rather than by conventional thermionic emission in MOSFETs. TFETs based on group III-V compound semiconductor and Ge heterostructures further improve the ON-state current and reduce SS due to the low bandgap energies and smaller carrier tunneling mass. The mixed arsenide/antimonide (As/Sb) InxGa1-xAs/GaAsySb1-y and Ge/InxGa1-xAs heterostructures allow a wide range of bandgap energies and various band alignments depending on the alloy compositions in the source and channel materials. Band alignments at source/channel heterointerface can be well modulated by carefully controlling the compositions of the InxGa1-xAs or GaAsySb1-y. In particular, this research systematically investigate the development and optimization of low-power TFETs using mixed As/Sb and Ge/InxGa1-xAs based heterostructures including: basic working principles, design considerations, material growth, interface engineering, material characterization, band alignment determination, device fabrication, device performance investigation, and high-temperature reliability. A comprehensive study of TFETs using mixed As/Sb and Ge/InxGa1-xAs based heterostructures shows superior structural properties and distinguished device performances, both of which indicate the mixed As/Sb and Ge/InxGa1-xAs based TFET as a promising option for high performance, low standby power and energy efficient logic circuit application. / Ph. D.

Nanotechnology offers great promise for the development of nanodevices. Hence it becomes important to study the mechanical behavior of nanostructures for their use in such systems. MEMS (Micro ElectroMechanical Systems) provide an effective and precise method for testing nanostructures. Consequently this study focuses on the development of a MEMS thermal nanotensile tester to investigate the mechanical behavior of one-dimensional nanostructures. Extensive characterization of these MEMS devices (structural, electrical and thermal behavior) was performed using experimental as well as finite element methods. Tensile testing of nanostructures requires manipulation of individual nanostructures on the MEMS device. The study involves the development of an efficient methodology for the manipulation of nanowires and nanobeams for nanoscale testing. Furthermore, two different sensing schemes for the developed devices, namely capacitive and resistive, have been extensively investigated and the advantages and various issues related to both have been discussed. Nanocrystalline (nc) Ni nanobeams (typical dimensions of 500 nm x 200 nm x 20 µm) have been tested to failure using the MEMS devices. Improvements in the design for the MEMS nanotensile tester have been suggested to significantly enhance the device performance and to resolve the various issues involved with nano scale tests. Differential capacitive sensing for stress-strain measurements has been suggested to improve the accuracy of strain measurements.

Ce travail de thèse présente une étude concernant la caractérisation des effets électrothermiques dans les transistors bipolaires à hétérojonction (HBT) en SiGe. Lors de ces travaux, deux procédés technologiques BiCMOS à l’état de l’art ont été analysés: le B11HFC de Infineon Technologies (130nm) et le B55 de STMicroelectronics (55nm).Des structures de test dédiées ont étés conçues, pour évaluer l’impact électrothermique du back end of line (BEOL) de composants ayant une architecture à un ou plusieurs doigts d’émetteur. Une caractérisation complète a été effectuée en régime continu et en mode alternatif en petit et en grand signal. De plus, une extraction des paramètres thermiques statiques et dynamiques a été réalisée et présentée pour les structures de test proposées. Il est démontré que les figures de mérite DC et RF s’améliorent sensiblement en positionnant des couches de métal sur le transistor, dessinées de manière innovante et ayant pour fonction de guider le flux thermique vers l’extérieur. L’impact thermique du BEOL a été modélisé et vérifié expérimentalement dans le domaine temporel et fréquentiel et aussi grâce à des simulations 3D par éléments finis. Il est à noter que l’effet du profil de dopage sur la conductivité thermique est analysé et pris en compte.Des topologies de transistor innovantes ont étés conçues, permettant une amélioration des spécifications de l’aire de sécurité de fonctionnement, grâce à un dessin innovant de la surface d’émetteur et du deep trench (DTI).Un modèle compact est proposé pour simuler les effets de couplage thermique en dynamique entre les émetteurs des HBT multi-doigts; ensuite le modèle est validé avec de mesures dédiées et des simulations TCAD.Des circuits de test ont étés conçus et mesurés, pour vérifier la précision des modèles compacts utilisés dans les simulateurs de circuits; de plus, l’impact du couplage thermique entre les transistors sur les performances des circuits a été évalué et modélisé. Finalement, l’impact du dissipateur thermique positionné sur le transistor a été étudié au niveau circuit, montrant un réel intérêt de cette approche. / This work is focused on the characterization of electro-thermal effects in advanced SiGe hetero-junction bipolar transistors (HBTs); two state of the art BiCMOS processes have been analyzed: the B11HFC from Infineon Technologies (130nm) and the B55 from STMicroelectronics (55nm).Special test structures have been designed, in order to evaluate the overall electro-thermal impact of the back end of line (BEOL) in single finger and multi-finger components. A complete DC and RF electrical characterization at small and large signal, as well as the extraction of the device static and dynamic thermal parameters are performed on the proposed test structures, showing a sensible improvement of the DC and RF figures of merit when metal dummies are added upon the transistor. The thermal impact of the BEOL has been modeled and experimentally verified in the time and frequency domain and by means of 3D TCAD simulations, in which the effect of the doping profile on the thermal conductivity is analyzed and taken into account.Innovative multi-finger transistor topologies are designed, which allow an improvement of the SOA specifications, thanks to a careful design of the drawn emitter area and of the deep trench isolation (DTI) enclosed area.A compact thermal model is proposed for taking into account the mutual thermal coupling between the emitter stripes of multi-finger HBTs in dynamic operation and is validated upon dedicated pulsed measurements and TCAD simulations.Specially designed circuit blocks have been realized and measured, in order to verify the accuracy of device compact models in electrical circuit simulators; moreover the impact on the circuit performances of mutual thermal coupling among neighboring transistors and the presence of BEOL metal dummies is evaluated and modeled.