International Telemetering Conference Proceedings / October 27-30, 1997 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Telemetry & Instrumentation, in conjunction with NASA’s Kennedy Space Center, has developed a commercial, intelligent, data acquisition module that performs all functions associated with acquiring and digitizing a transducer measurement. These functions include transducer excitation, signal gain and anti-aliasing filtering, A/D conversion, linearization and digital filtering, and sample rate decimation. The functions are programmable and are set up from information stored in a local Transducer Electronic Data Sheet (TEDS). In addition, the module performs continuous self-calibration and self-test to maintain 0.01% accuracy over its entire operating temperature range for periods of one year without manual recalibration. The module operates in conjunction with a VME-based data acquisition system.

Dans cette thèse, les recherches ont été menées à des niveaux d'abstraction différents pour optimiser le fonctionnement du modulateur ΣΔ passe-haut (PH). Une approche « top-down » est adoptée pour atteindre cet objectif. Au niveau de l'architecture du récepteur RF, le nouvellement créé récepteur Fs/2 est sélectionné pour sa grande compatibilité avec modulateur ΣΔ PH comparé aux architectures de réception: zéro-IF et faible-IF. Après avoir défini la topologie du récepteur, l'architecture du modulateur ΣΔ est adressée. Nous proposons une nouvelle architecture du deuxième ordre dont la fonction de transfert du signal est unitaire. Elle est plus avantageuse que d'autres topologies en termes de complexité et de performance. Puisque le modulateur de second ordre est incapable de fournir les performances requises, les structures en cascade ou MASH pour l'opération PH sont explorées. La topologie GMSCL (Generalized Multi-Stage Closed Loop) est choisie et une technique récemment proposée est appliquée pour linéariser le CNA de retour. En plus, cette technique augmente la plage dynamique du convertisseur. Ensuite, après une analyse comparative approfondie, le meilleur filtre HP est choisie pour ce modulateur. Il a les avantages d'avoir une basse consommation, une superficie réduite et un bruit moins important. Enfin, l'architecture GMSCL PH proposée est validée en CMOS 65nm. Les applications visées sont l'UMTS avec 3.84MHz bande de conversion à 80 dB de la plage dynamique et WiMAX avec 25MHz de bande passante à 52dB de dynamique.

Cette thèse est le fruit d'un partenariat entre la BL TVFE de NXP Semiconductors et l'ESIEE dans le cadre d'une thèse CIFRE. Le but est d'apporter une solution qui permette la réception de plusieurs canaux pour le câble. Ce sujet est lié à la problématique de numérisation large bande. Dans la première partie, nous faisons un état-de-l'art sur les convertisseurs analogiques-numériques (CAN), sur les architectures parallèles (entrelacement temporel et bancs de filtres hybrides (BFH)), et sur les méthodes d'échantillonnage (passe-bande et complexe). Puis, nous étudions une architecture composée d'un banc de filtres analogiques et un banc de CANs. Nous cherchons à réduire surtout le taux d'échantillonnage. Nous comparons notre solution à un CAN large bande performant, avec notre fonction de coût. L'un des avantages de cette architecture est que tous les composants sont faisables, même les CANs, et qu'il est possible d'éteindre des sous-bandes pour diminuer la consommation. Cette solution est intéressante pour le moment mais n'est pas compétitive en termes de consommation et de surface. Nous proposons une alternative dans la partie 3, avec les BFH. Nous étudions cette architecture, en gardant à l'esprit la faisabilité de la solution. Nous avons choisi un BFH à deux voies, avec un filtre analogique passe-bas et un passe-haut. Puis, nous proposons un algorithme d'optimisation des filtres de synthèse pour atteindre nos objectifs de distorsion et de réjection de repliement. Une identification des filtres analogiques est aussi présentée. Finalement, une réalisation physique prouve le concept et valide les limitations théoriques de cette architecture / This thesis is a partnership between the BL TVFE of NXP Semiconductors and ESIEE. Its goal is to provide a solution to multi-channel reception for cable network. This is linked to the problematic of broadband digitization. In the first part, the state-of-the art of ADCs, parallel architectures (TI and HFB) and sampling methods (bandpass sampling and complex sampling) is recalled. Then we study an architecture called RFFB with a bank of analog filters and a bank of ADCs. We try to reduce the constraints on ADCs, especially the sampling rate with the different sampling. We propose an interesting solution to broadband digitization and compare this solution to a challenging wideband ADC, using the cost function we introduce. This architecture has the major advantage that all the components are feasible, even the ADCs, and it is possible to switch-off subbands to save power. It could be a good solution at the present time but it is not competitive in terms of power consumption and surface. An alternative is proposed in Part 3, where we study Hybrid Filter Banks. It is interesting to study this architecture with realization feasibility in mind. This is why we select a 2-channel HFB with a lowpass filter and a highpass filter as analog filters. Then we propose an efficient optimization algorithm to find the best synthesis filters and reach our targets of distortion and aliasing rejection. An identification of analog filters is also suggested to cope with the issue of sensitivity to analog errors. Finally, a physical realization proves the concept of aliasing rejection and confirms the theoretical issues of this architecture

Resolver, due to its reliability and durability, has been used for the aim of shaft position sensing of military rotary systems such as tank turrets and gun stabilization platforms for decades. Ready-to-use resolver-to-digital converter integrated circuits which convert the resolver signals into position and speed measurements are utilized in servo systems most commonly. However, the ready-to-use integrated circuits increase the dependency of the servo system to hardware components which in turn decrease the efficiency and flexibility of the servo system for changing system structures such as for changing resolver carrier frequency or changing position and speed sensors. The proposed solution to increase the efficiency and flexibility of the servo system is a software-based resolver-to-digital converter which does not require aforesaid special hardware components and presents a complete software-based solution for the conversion. The proposed software-based resolver-to-digital converter makes use of common programmable hardware v components, that is, FPGA and DSP which form the heart of the servo controller technology in recent years. The proposed structure for the conversion has three components. The first component is the signal conditioner which minimizes the disturbances coming from the resolver signals as harmonic distortions and noise. The second component, the phase-sensitive demodulator, as the name implies, is responsible for phase-sensitive demodulation of resolver signals. The third component is the estimator filter. In order to determine the optimal estimator filter, five different estimator filters with the aforesaid two components are implemented in ASELSAN&rsquo / s stabilized gun system STAMP and they are compared in terms of both estimation performance and computational complexity. The implemented filters include nonlinear observer type filter which is already proposed in the literature for resolver conversion, tracking differentiator adapted to resolver conversion and kalman filters adapted to resolver conversion in different forms such as linear kalman filter, extended kalman filter and unscented kalman filter. At the end of the study, stability and sensitivity analyses are also performed for the proposed system.

Face aux défis actuels liés à la conception de capteurs d'images à forte résolution comme la limitation de la consommation électrique, l'augmentation du flux de données ainsi que le traitement de données associé, on propose, à travers cette thèse, un capteur d'image novateur asynchrone à échantillonnage non uniforme.Ce capteur d’images asynchrone est basé sur une matrice de pixels événementiels qui intègrent un échantillonnage non uniforme par traversée de niveaux. Contrairement aux imageurs conventionnels, où les pixels sont lus systématiquement lors de chaque trame, les pixels événementiels proposés sont consultés que lorsqu’ils contiennent une information pertinente. Cela induit un flux de données réduit et dépendant de l’image.Pour compléter la chaîne de traitement des pixels, on présente également une architecture numérique de lecture dédiée conçue en utilisant de la logique asynchrone et destinée à contrôler et à gérer le flux de données des pixels événementiels. Ce circuit de lecture numérique permet de surmonter les difficultés classiques rencontrées lors de la gestion des demandes simultanées des pixels événementiels sans dégrader la résolution et le facteur de remplissage du capteur d’images. En outre, le circuit de lecture proposé permet de réduire considérablement les redondances spatiales dans une image ce qui diminue encore le flux de données.Enfin, en combinant l'aspect échantillonnage par traversée de niveau et la technique de lecture proposée, on a pu remplacer la conversion analogique numérique classique de la chaîne de traitement des pixels par une conversion temps-numérique (Time-to-Digital Conversion). En d'autres termes, l'information du pixel est codée par le temps. Il en résulte une diminution accrue de la consommation électrique du système de vision, le convertisseur analogique-numérique étant un des composants les plus consommant du système de lecture des capteurs d'images conventionnels / In order to overcome the challenges associated with the design of high resolution image sensors, we propose, through this thesis, an innovative asynchronous event-driven image sensor based on non-uniform sampling. The proposed image sensor aims the reduction of the data flow and its associated data processing by limiting the activity of our image sensor to the new captured information.The proposed asynchronous image sensor is based on an event-driven pixels that incorporate a non-uniform sampling crossing levels. Unlike conventional imagers, where the pixels are read systematically at each frame, the proposed event-driven pixels are only read when they hold new and relevant information. This induces a reduced and scene dependent data flow.In this thesis, we introduce a complete pixel reading sequence. Beside the event-driven pixel, the proposed reading system is designed using asynchronous logic and adapted to control and manage the flow of data from event pixels. This digital reading system overcomes the traditional difficulties encountered in the management of simultaneous requests for event pixels without degrading the resolution and fill factor of the image sensor. In addition, the proposed reading circuit significantly reduces the spatial redundancy in an image which further reduces the data flow.Finally, by combining the aspect of level crossing sampling and the proposed reading technique, we replaced the conventional analog to digital conversion of the pixel processing chain by a time-to-digital Conversion (TDC). In other words, the pixel information is coded by time. This results in an increased reduction in power consumption of the vision system, the analog-digital converter being one of the most consuming reading system of conventional image sensors components

Orientador: Frab Norberto Bóscolo / Tese (doutorado) - Universidade Estadual de Campinas, Faculdade de Odontologia de Piracicaba / Made available in DSpace on 2018-08-22T13:39:06Z (GMT). No. of bitstreams: 1 Frazao_MarcoAntonioGomes_D.pdf: 4262109 bytes, checksum: 0e3256f8a0dd02738990d526d5a2329b (MD5) Previous issue date: 2012 / Resumo: Com este estudo, teve-se a proposta de avaliar a modificação da densidade de 4 cores (branco, cinza claro, cinza escuro e preto) em filmes radiográficos impressos por duas tecnologias dry seca: termográfica (AGFA) e fototermográfica (KODAK). Para isso, foi utilizada uma amostra formada por 18 grupos com 6 corpos de prova para cada uma das tecnologias de impressão totalizando um experimento com 216 corpos de prova submetidos às temperaturas de 40ºC, 60ºC e 80ºC, pelos tempos de 30, 60 e 120 minutos com e sem a exposição solar. Nestes foram realizadas analises densitométricas antes e depois da exposição aos fatores estudados e os dados obtidos submetidos aos testes estatísticos de: Kruskal Wallis, Mann-Whitney e Wilcoxon para dados pareados com nível de significância de 5%. Pôde-se observar que as cores avaliadas impressas no filme pela tecnologia termográfica (AGFA) modificam sua densidade a partir de combinações de exposição a 60ºC e 120 minutos e a 80ºC e 30 minutos sem a exposição ao sol e a partir de 40ºC e 30 minutos com exposição solar, e no filme impresso pela tecnologia fototermográfica (KODAK) modifica sua densidade a 40ºC a partir de 30 minutos com e sem a exposição solar. Concluiu-se que o aumento da temperatura de armazenamento bem com a exposição à luz solar modificam a densidade dos filmes radiográficos impressos pelas tecnologias dry seca avaliadas / Abstract: The purpose of this study was to evaluate the density modification of 4 colors (white, light gray, dark gray and black) in films printed by two dry technologies: thermographic (AGFA) and photothermographic (KODAK). A sample consisting of 18 groups with six specimens per printing technologies was used, totaling an experiment of 216 evaluated specimens when subjected to temperatures of 40°C, 60°C and 80°C, for periods of 30, 60 and 120 minutes with and without sunlight exposure. These specimens were submitted to densitometric analysis before and after exposure to the studied factors and data were subjected to the following statistical tests: Kruskal Wallis, Mann-Whitney and Wilcoxon for paired data. It was observed that the evaluated colors printed on the film by thermographic technology (AGFA) modify their density at exposures to 60°C and 120 minutes, and without sunlight exposure at the temperature of 80°C after 30 minutes, and with sunlight exposure from 40°C and 30 minutes, and the film printed by photothermographic technology (KODAK) modifies its density at 40°C from 30 minutes with and without sunlight exposure. It was concluded that the increase of storage temperature and sunlight exposure modify the density of radiographic films printed by dry technologies / Doutorado / Radiologia Odontologica / Doutor em Radiologia Odontológica

High precision tightening of nuts and bolts together with traceability are important in many industrial assembly lines. To achieve this the nutrunner needs to accurately measure the torque which is applied to the nut, process the signal and provide the information to the controller that controls the tightening process. This is done by having a strain gauge in form of a Wheatstone bridge connected to the tightening shaft. When an excitation voltage is applied to the bridge the applied torque to the shaft can be measured in form of a voltage difference. This voltage is amplified, filtered and converted to a digital signal, this is referred to as the signal chain. Atlas Copco has provided an example of how the signal chain looks in today’s application. The signal chain consists of a gain stage and a filter stage, and the analog-to-digital conversion process is performed internally in an MCU together with several advanced digital filters. The purpose of this thesis is to analyse this signal chain, it’s performance in regards to noise and investigate if the chain can be redesigned with the same or better noise performance with other components. It should also be investigated if the conversion process can be moved from the MCU to an integrated circuit component to reduce the effects of noise from the tool motor. Hence, in addition to noise, other specifications such as power supply and physical footprint is also considered in the thesis. The goal is to define a process on how to analyse the noise, precision, speed and footprint in a front end signal chain. In addition to that, one or more alternative signal chains should be presented if the requirements of the front end can be fulfilled. A lot of effort went into researching how noise impacts a signal chain to get a thorough understanding on how to improve/rebuild an already functioning signal chain. The result was a working process on how to analyse the noise in a front end signal chain like the one described above, together with a generic noise simulation model in LTSpice which can be used if a component does not have a spice model. With the model a few alternative signal chains were considered which fulfills the noise requirements and the best performing alternative was built on a PCB in KiCAD. However, the physical PCB has not been tested due to the limited timeframe of the project and therefore only calculations and simulations act as the verifying element of the function. / Högprecisionsåtdragning av skruvar och bultar är en viktig del av många industriella tillverkningsprocesser. I detta ingår ofta spårbarhet som en viktig del för att kunna kvalitetssäkra processerna. För att åstadkomma detta måste skruvdragaren kunna mäta det moment som appliceras vid en åtdragning, bearbeta denna signal och tillhandahålla den till kontrollenheten som styr åtdragningsprocessen. Momentmätningen görs med en töjningsgivare, ofta av typen Wheatstonebrygga, som kopplas till verktygets axel. När en excitationsspänning kopplas till bryggan kan momentkraften i axeln mätas i form av en spänningsskillnad. Denna analoga signal blir sedan förstärkt, filtrerad och omvandlad till en digital signal. Denna process benämns som signalkedjan. Företaget har tillhandahållit ett exempel på hur en sådan signalkedja ser ut i en av deras nuvarande verktyg. I dagens utförande sker signalomvandlingen internt i en mikrokontroller, där den också filtreras med digitala filter. Syftet med denna avhandling är att analysera signalkedjan, dennas prestation i förhållande till brus, och undersöka ifall signalkedjan kan återskapas med samma eller bättre brusegenskaper med andra komponenter. Det undersöks även om signalomvandlingen kan flyttas från mikrokontrollern till en integrerad krets-komponent för att minska signalens påverkan från brus från verktygets motor. Som led i detta kommer även kretsens fysiska fotavtryck undersökas då det styr var på verktyget kretsen kan monteras. Målet är att definiera en process för att analysera brus, precision, hastighet och fotavtryck i ett signalgränssnitt av denna typ. Utöver detta skall en eller flera förslag till alternativa signalkedjor presenteras om de kan uppfylla kraven på gränssnittet. Mycket ansträngning gick till att undersöka hur brus påverkar en signalkedja för att få en grundlig förståelse av hur man kan förbättra och/eller bygga om en befintlig signalkedja. Resultatet blev en fungerande teoretisk analysprocess av brus i en signalkedja i ett gränssnitt av den typen som beskrivs ovan. Ytterligare resultat var en generell brussimuleringsmodell i LTSpice som kan användas då en komponent saknar Spice-modell. Med hjälp av modellen utvärderades några alternativa signalkedjor utifrån deras brusegenskaper och utifrån det bästa alternativet togs en PCB-layout fram i KiCad. Några tester på en fysisk krets har dock inte gjorts då tidsramen för projektet inte tillät tillverkning av kretskortet. Därför utgår utvärderingen av kretsens funktion enbart från teoretiska beräkningar och simuleringar.

Neste trabalho é apresentado o desenvolvimento de instrumentação eletrônica para controle e automação de um sistema de crescimento de semicondutores por Epitaxia por Feixes Moleculares. Envolve uma variedade de circuitos analógicos e digitais como: um módulo de aquisição de dados e controle baseado em uma UCP Z-80, contendo algumas interfaces digitais e analógicas multiplexadas, e comunicando-se com um microcomputador através de uma interface serial. Envolve ainda o desenvolvimento de controladores de temperatura analógicos tipo P.I.D., atuação por motores de passo e circuitos de condicionamento de sinal. / In this work is presented the development of electronic instrumentation for automation and control of a Molecular Beam Epitaxy semiconductor growth system. A variety of analog and digital instrumentation circuits have been designed and implemented, including a data acquisition and control system based on a Z-80 CPU, which controls some multiplexed digital and analog interfaces and talks to a microcomputer using serial communication. Other circuits have been also developed, including analog temperature controllers, stepper motor actuators and circuits for signal conditioning.

Le Convertisseur Analogique Numérique (CAN) est une brique essentielle de la ré- ception et du traitement des données à très haut débit. L’architecture de type "flash" effectue la quantification en comparant simultanément le signal analogique d’entrée à l’ensemble des références du codeur, ce qui en fait, par construction, l’architecture la plus rapide de CAN. Par le passé, cette architecture a démontré des capacités de codage supérieures à 20GS/s dans les conditions de Nyquist. Cependant, cette capac- ité à travailler à très haute vitesse a donné le jour à des réalisations très consommantes (plusieurs Watts) donc peu efficaces énergétiquement. Cette thèse explore différentes approches d’optimisation de l’efficacité énergétique des CAN "flash". Afin de min- imiser la consommation du CAN, il n’y a pas d’Echantillonneur-Bloqueur (EB) en tête du circuit. Les étages d’entrée du codeur sont ainsi exposés à la pleine bande passante du signal, à savoir DC-10GHz. Ceci impose des contraintes très strictes sur la précision temporelle de la détection et de la quantification du signal. L’essentiel de cette thèse est donc concentré sur l’analyse des effets hautes frèquences impactant la conception des éléments frontaux du CAN. La validité et l’efficacité des méthodes présentées sont démontrées par des mesures autour d’un CAN 6 bit 20 GS/s. En em- pruntant les techniques de conception des circuits ultra-rapides et en exploitant le po- tentiel haute-fréquence de la technologie à l’état de l’art SiGe BiCMOS, un circuit complètement analogique a ainsi pu être réalisé. Ce CAN est mono-voie et n’a besoin d’aucune calibration ou correction, ni d’assistance digitale. Avec à peine 1W, ce cir- cuit atteint un record d’efficacité énergétique dans l’état de l’art des CAN rapides non entrelacés. / High speed Analog-to-Digital Converters (ADC) are essential building blocks for the reception and processing in high data rate reception circuits. The flash ADC archi- tecture performs the digitization by comparing the analog input signal to all refer- ence levels of the quantization range simultaneously and is thus the fastest architecture available. In the past the flash architecture has been employed successfully to digitize signals at Nyquist rates beyond 20 GS/s. However the inherent high speed operation has led to power consumptions of several watts and hence to poor energy efficien- cies. This thesis explores approaches to optimize the energy efficiency of flash ADCs. In particular, no dedicated track-and-hold stage is used at the high speed data input. This imposes very stringent requirements on the timing accuracy and level accuracy in the high speed signal distribution to the comparators. The comparators need to ex- hibit a very high speed capability to correctly perform the quantization of the signal against the reference levels. The main focus of this thesis is hence the investigation of design relevant high frequency effects in the analog ADC frontend, such as the bandwidth requirement of overdriven comparators, the data signal distribution over a passive transmission line tree and the dynamic linearity of emitter followers. The correctness and efficacy of the presented methods is demonstrated by measurement results of a 6 bit 20 GS/s Nyquist rate flash ADC fabricated within the context of this work. The demonstrator ADC operates without time interleaving, no calibration or correction whatsoever is needed. By employing design techniques borrowed from high speed analog circuits engineering and by exhausting the high speed potential of a state-of-the-art SiGe BiCMOS production technology, a flash ADC with a record energy efficiency could be realized.

Der Tagungsband beschäftigt sich mit den aus den neuen Technologien erwachsenden Anforderungen an die Archive. Er fasst mehrere Aufsätze zusammen, die sich aus unterschiedlichen Perspektiven mit diesen Herausforderungen beschäftigen. Das Eingangsreferat von Norbert Becker wertet eine Umfrage zu Erwartungen der Benutzer im Hinblick auf die modernen Medien und Informationstechnologien aus. Kerstin Arnold stellt das Projekt zur Schaffung eines Archivportals für die Bundesrepublik Deutschland vor. In zwei weiteren Beiträgen werden konkrete Digitalisierungsprojekte bzw. –strategien vorgestellt. Susanne Knoblich, Berlin, stellt einen Werkstattbericht zur Übernahme von elektronischen Unterlagen in das Landesarchiv Berlin vor. Abgerundet wird der Band durch einen Beitrag von Kerstin Orantek zu den Problemen des Datenschutzes in einer digitalisierten Welt. / The proceedings of the conference are concerned with the requirements for archives arising due to new technologies. It comprises several papers addressing these challenges from different perspectives. The opening address by Norbert Becker evaluates a survey on user expectations concerning modern media and information technologies. Kerstin Arnold describes a project to create the archive portal of the Federal Republic of Germany. In two other contributions, specific digitisation projects or strategies are discussed. Susanne Knoblich from Berlin presents a working report on the transfer of electronic documents for the National Archives of Berlin. Kerstin Orantek completes the volume with a contribution on the problem of data protection in a digital world.