Delta-sigma data converters have gained popularity in both analog-to-digital and digital-to-analog converters (ADCs and DACs) due to their simplicity, high linearity and immunity to many analog circuit imperfections. These data converters include features such as oversampling, noise-shaping, and (historically) single-bit quantization. Single-bit converters are preferred for their inherent linearity. This is a feature which multibit converters cannot realize due to the unavoidable phenomenon of element mismatch. Because of this problem, multibit converters have been largely unexplored, and the market has seen few multibit commercial products. Earlier work has shown that multibit DACs constructed with unit elements can be applied in an architecture which shapes the spectrum of the noise caused by element mismatch. The basis of this thesis is the experimental verification of such a DAC. A Xilinx 4005 FPGA is utilized to implement a 3rd-order 4-bit delta-sigma modulator and the mismatch-shaping logic, while a custom IC consisting of 16 individually-controlled differential current sources implements the unit-element DAC. The final DAC achives a Spurious Free Dynamic Range (SFDR) of 96 dB at a sampling rate of 62.5 kHz. / Graduation date: 1997

Decision Feedback Equalization (DFE) in a data recovery channel filters the bit decision in the current symbol period in generating the sample at the comparator in the subsequent clock period. The operations of sampling, comparing, filtering the decision bits into a feedback signal, and subtraction of that feedback signal are cascaded, thereby establishing the critical timing path. Thus, this system, though simple, requires its components to have large bandwidths in order to achieve the high-speed response necessary to perform the described feedback function. For the entire system to run at speeds comparable to those of competing technologies (100MHz to 250MHz), the components must have bandwidths greater than 100MHz, and work together to provide a loop bandwidth of at least 100MHz. A 300MHz latching comparator and a 125MHz 6-bit current-DAC were designed in a 5V, 1 um CMOS n-well process for use in a DFE loop. Both blocks are fully differential and achieve an accuracy of 1/2 LSB (10uA) over a differential signal range of 1.28mA. This is true for their operations at speed, in isolated simulation and as contiguous blocks. The DAC power consumption is relatively high at 23mW, due to internal switching circuits which require a static current, but the comparator's power consumption is minimal at 5mW. / Graduation date: 1997

Graduation date: 1994

Thesis (M.A.)--Kutztown University of Pennsylvania, 2000. / Source: Masters Abstracts International, Volume: 45-06, page: 2707. Typescript. Abstract precedes thesis title page as [2] preliminary leaves. Copy 2 in Main Collection. Includes bibliographical references (leaves 108-115).

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This thesis presents a stable technique for distribution of data in Time Interleaved Digital-to-Analog Converters (TIDAC) that allows usage of the entire Nyquist bandwidth. The data distribution uses a Thiran all-pass filter to ensure stability and preserve the phase in the bandwidth of interest. Also, an online technique to compensate for the gain error mismatch in different channels and a skew error calibration technique for open loop configuration is proposed. For the over-all sampling rate of FS, i.e. bandwidth of FS/2 (according to Nyquist), this proposed technique allows calibration of skew error for input signal for most of the Nyquist bandwidth where frequency translation is applied to the input signal to provide calibration in the lower half of the Nyquist band. The simulation results for a 2-channel 14-bit current steering binary weighted TIDAC shows a substantial improvement in SNDR after calibration for input signals up to Nyquist frequency.

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Thesis (M.S.)--Oregon State University, 2006. / Printout. Includes bibliographical references (leaves 55-58). Also available on the World Wide Web.

Thesis (Ph. D.)--Washington State University, August 2006. / Includes bibliographical references (p. 77-79).