Thesis (Ph. D.)--Oregon State University, 2008. / Printout. Includes bibliographical references. Also available on the World Wide Web.

Thesis (Ph.D.) - Carleton University, 2007. / Includes bibliographical references (p. 111-116). Also available in electronic format on the Internet.

Thesis (Ph. D.)--Carleton University, 1999. / Also available in electronic format on the Internet.

Thesis (M.S.)--Oregon State University, 2006. / Printout. Includes bibliographical references (leaves 104-107). Also available on the World Wide Web.

Thesis (M.S.)--University of Wisconsin--Madison, 1969. / eContent provider-neutral record in process. Description based on print version record.

This thesis treats broad aspects of voltage-to-digital converter design. Particular emphasis is placed on material related to designing a converter to satisfy a set of converter specifications that is given in the introduction of the thesis. The converter design is first considered in terms of basic conversion techniques. One technique, known as"successive approximation,” seems best to satisfy the requirements of the design specifications. The “successive-approximation" voltage-to-digital converter requires that its input voltage be compared to a voltage that is systematically generated within the converter. The voltage generated within the converter is derived from digital information. When the internal voltage equals the external applied voltage, a conversion is accomplished and the converter can output its digital information as the numerical equivalent of its input voltage. A major part of the thesis is concerned with basic approaches that might be used in generating a voltage from digital information in a manner that is fast, accurate, stable, and compatible with a fast, accurate, stable comparison operation. Another major part of the thesis presents analysis of specific circuits that are used in the construction of a converter designed to satisfy the introduction’s specifications. A report on the performance of a converter built with the just mentioned circuits is included. / Master of Science

In an increasingly digital world, the need for high speed and high fidelity analog-to-digital (A/D) converters is paramount. Performance improvements in electronic A/Ds have not kept pace with demand, hence the need to consider alternative technologies. One such technology is photonics, as it takes advantage of optical sampling, high speed optical switches and low cross-talk interconnects. Optical sampling derives its advantage from the application of ultra low timing jitter (<100fs) mode locked lasers utilised to provide high speed clock pulses. In this thesis the feasibility and simulated performance of three different types of photonic oversampled A/D converters was investigated. The first, and simplest design is that of oversampled pulse-code-modulation (PCM), where a 2-level photonic comparator is used to sample the analog input at a frequency much greater than the Nyquist frequency. Subsequent low pass filtering produces a digital representation of the input. The other two architectures that were investigated are the first-order sigma-delta and error diffusion, which add one level of error correction to the PCM technique. These two architectures require the functional elements of a subtractor, comparator and delay. The photonic comparator and subtractor functionality was provided by Self-Electro-Optic Effect devices (SEED) based upon multiple quantum well (MQW) p-i-n devices. To facilitate calculation of the performance of the different architectures and aid in device design, a simulation of SEED operation based upon experimental data was developed. The simulation’s accuracy was demonstrated by agreement with the results from experimental S-SEED switching and optical subtraction. To emphasize the utility of the model, the simulation was subsequently used to demonstrate tristability of an S-SEED and critical slowing down in a bistable S-SEED. These effects were experimentally verified. To provide enhanced comparator contrast ratio and subtractor dynamic range, resonantly enhanced microcavity multiple quantum well (MQW) p-i-n devices were designed and grown by MOCVD. The operation of the subtractor and comparator was experimentally demonstrated and utilising temperature tuning, optimised performance was achieved with devices from the same wafer. Furthermore, the inclusion of gain was shown to improve the subtractor performance to that demanded by the sigma-delta. The constraints on each architecture imposed by the unipolar nature of the light intensity were derived and the sigma delta architecture was shown to be superior to the error diffusion for a photonic implementation. Using the numerical simulation based upon experimentally derived data, the entire sigma delta architecture was simulated to calculate the expected performance. The signal-to-quantisation-noise ratio (SQNR) was calculated as a function input amplitude and a peak SQNR of 54dB was obtained for an oversampling ratio of 100. / http://library.adelaide.edu.au/cgi-bin/Pwebrecon.cgi?BBID=1283979 / Thesis (Ph.D.) -- University of Adelaide, School of Chemistry and Physics, 2007

Graduation date: 2006 / The design of a 10-bit pipelined charge redistribution DAC employing MOSCAPs biased in their accumulation mode is presented in this thesis. A switched capacitor filter and output buffer have also been designed for the system. The effect of MOSCAP nonlinearity on the performance of the pipelined charge redistribution DAC has been analyzed. MOS capacitors and their models available for simulation have been discussed. In addition, the effect of more general capacitor nonlinearities on the performance of the DAC has been presented.

In this thesis work, a design of 14-bit, 20MS/s segmented digital-to-analog converter (DAC) is presented. The segmented DAC uses switched-capacitor configuration to implement 8 (LSB) + 6 (MSB) segmented architecture to achieve high performance for minimum area. The implemented LSB DAC is based on quasi-passive pipelined DAC that has been proven to provide low power and high speed operation. Typically, capacitor matching is the best among all integrated circuit components but the mismatch among nominally equal value capacitors will introduce nonlinear distortion. By using dynamic element matching (DEM) technique in the MSB DAC, the nonlinearity caused by capacitor mismatch is greatly reduced. The output buffer employed direct charge transfer (DCT) technique that can minimize kT/C noise without increasing the power dissipation. This segmented DAC is designed and simulated in 0.18 μm CMOS technology, and the simulated core DAC block only consumes 403 μW. / Graduation date: 2012

High-speed digital-to-analog converters are critical components in many radiofrequency (RF) applications. The resistive DAC (RDAC) architecture is suitable for high-speed implementation in extremely scaled digital circuit nodes. An RDAC core can be implemented as a resistance network and a digital block, consisting of inverters as drivers to the resistive network. One disadvantage of the architecture is the input code-dependent supply current. Combined with a non-zero supply network impedance, the code-dependent current will introduce non-linearity in the output voltage. One way to circumvent the problem is to use a high-performance voltage regulator, which counteracts the voltage variation in the impedance in the RDAC supply network. In this thesis work, two alternative solutions are investigated; Compensation with another signal-dependent impedance in parallel with the RDAC core to reduce the impedance variations and a digital predistorter (DPD) which corrects the non-linearities of RDAC output voltage. The investigated techniques can be used for improving the linearity of an RDAC in certain cases. The current compensation technique works best at low frequencies, while the DPD can be used for all frequencies to relax requirements on routing resistance or voltage regulation design.