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Digital signal processing (DSP) is widely used in many applications spanning the spectrum from audio processing to image and video processing to radar and sonar processing. At the core of digital signal processing applications is the digital filter which are implemented in two ways, using either finite impulse response (FIR) filters or infinite impulse response (IIR) filters. The primary difference between FIR and IIR is that for FIR filters, the output is dependent only on the inputs, while for IIR filters the output is dependent on the inputs and the previous outputs. FIR filters also do not sur from stability issues stemming from the feedback of the output to the input that aect IIR filters. In this thesis, an architecture for FIR filtering based on distributed arithmetic is presented. The proposed architecture has the ability to implement large FIR filters using minimal hardware and at the same time is able to complete the FIR filtering operation in minimal amount of time and delay when compared to typical FIR filter implementations. The proposed architecture is then used to implement the fast affine projection adaptive algorithm, an algorithm that is typically used with large filter sizes. The fast affine projection algorithm has a high computational burden that limits the throughput, which in turn restricts the number of applications. However, using the proposed FIR filtering architecture, the limitations on throughput are removed. The implementation of the fast affine projection adaptive algorithm using distributed arithmetic is unique to this thesis. The constructed adaptive filter shares all the benefits of the proposed FIR filter: low hardware requirements, high speed, and minimal delay.

This research focuses on a novel integrated approach for computing and representing complex numbers as a single entity without the use of any dedicated multiplier for calculating the fast Fourier transform algorithm (FFT), using the Distributed Arithmetic (DA) technique and Complex Binary Number Systems (CBNS). The FFT algorithm is one of the most used and implemented technique employed in many Digital Signal Processing (DSP) applications in the field of science, engineering, and mathematics. The DA approach is a technique that is used to compute the inner dot product between two vectors without the use of any dedicated multipliers. These dedicated multipliers are fast but they consume a large amount of hardware and are quite costly. The DA multiplier process is accomplished by shifting and adding only without the need of any dedicated multiplier. In today's technology, complex numbers are computed using the divide and conquer approach in which complex numbers are divided into two parts: the real and imaginary. The CBNS technique however, allows for each complex addition and multiplication to be computed in one single step instead of two. With the combined DA-CBNS approach for computing the FFT algorithm, those dedicated multipliers are being replaced with a DA system that utilize a Rom-based memory for storing the twiddle factor 'wn' value and the complex arithmetic operations being represented as a single entity, not two, with the CBNS approach. This architectural design was implemented by coding in a very high speed integrated circuit (VHSIC) hardware description language (VHDL) using Xilinx ISE design suite software program version 14.2. This computer aided tool allows for the design to be synthesized to a logic gate level in order to be further implemented onto a Field Programmable Gate Array (FPGA) device. The VHDL code used to build this architecture was downloaded on a Nexys 4 DDR Artix-7 FPGA board for further testing and analysis. This novel technique resulted in the use of no dedicated multipliers and required half the amount of complex arithmetic computations needed for calculating an FFT structure compared with its current traditional approach. Finally, the results showed that for the proposed architecture design, for a 32 bit, 8-point DA-CBNS FFT structure, the results showed a 32% area reduction, 41% power reduction, 59% reduction in run-time, 42% reduction in logic gate cost, and 66% increase in speed. For a 28 bit, 16-point DA-CBNS FFT structure, its area size, power consumption, run-time, and logic gate, were also found to be reduced at approximately 30%, 37%, 60%, and 39%, respectively, with an increase of speed of approximately 67% when compared to the traditional approach that employs dedicated multipliers and computes its complex arithmetic as two separate entities: the real and imaginary.

With the downscaling trend in CMOS technology, it has been possible to utilize the advantages of high element densities in VLSI circuits and systems. This trend has readily allowed digital circuits to predominate VLSI implementations due to their ease of scaling. However, high element density in integrated circuit technology has also entailed a decrease in the power consumption per functional circuit cell for the use of low-power and reconfigurable systems in portable equipment. Analog circuits have the advantage over digital circuits in designing low-power and compact VLSI circuits for signal processing systems. Also, analog circuits have been employed to utilize the wide dynamic range of the analog domain to meet the stringent signal-to-noise-and-distortion requirements of some signal processing applications. However, the imperfections and mismatches of CMOS devices can easily deteriorate the performance of analog circuits when they are used to realize precision and highly linear elements in the analog domain. This is mainly due to the lack of tunability of the analog circuits that necessitates the use of special trimming or layout techniques. These problems can be alleviated by making use of the analog storage and capacitive coupling capabilities of floating-gate transistors. In this research, tunable resistive elements and analog storages are built using floating-gate transistors to be incorporated into signal processing applications. Tunable linearized resistors are designed and implemented in CMOS technology, and are employed in building a highly linear amplifier, a transconductance multiplier, and a binary-weighted resistor digital-to-analog converter. Moreover, a tunable voltage reference is designed by utilizing the analog storage feature of the floating-gate transistor. This voltage reference is used to build low-power, compact, and tunable/reconfigurable voltage-output digital-to-analog converter and distributed arithmetic architecture.

When computational resources are limited, especially multipliers, distributed arithmetic (DA) is used in lieu of the typical multiplier-based filtering structures. However, DA is not well suited for adaptive applications. The bottleneck is updating the memory table. Several attempts have been done to accelerate updating the memory, but at the expense of additional memory usage and of convergence speed. To develop an adaptive DA filter with an uncompromised convergence rate, the memory table must be fully updated. In this research, an efficient method for fully updating a DA memory table is proposed. The proposed update method is based on exploiting the temporal locality of the stored data and subexpression sharing. The proposed update method reduces the computational workload and requires no additional memory resources. DA using the proposed update method is called conjugate distributed arithmetic. Filters can also be constructed from analog components. Often, for lower precision computations, analog circuits use less power and less chip area than their digital counterparts. However, digital components are often used because of their ease of reprogrammability. Achieving such reprogrammability in analog is possible, but at the expense of additional chip area. A reprogrammable mixed-signal DA finite impulse response (FIR) filter is proposed to address the issues with reprogrammable analog FIR filters that are constructing compact reprogrammable filtering structures, non-symmetric and imprecise filter coefficients, inconsistent sampling of the input data, and input sample data corruption. These issues are successfully addressed using distributed arithmetic, digital registers, and epots. Also, a mixed-signal DA second-order section (SOS), which is used as the building block for higher order infinite impulse response filters, was proposed. The type of issues with an analog SOS filter are similar to those of an analog FIR filter, which are the lack of a compact reprogrammable filtering structure, the imprecise filter coefficients, the inconsistent sampling of the data, and the corruption of the data samples. These issues are successfully addressed using distributed arithmetic and digital registers.