Indiana University-Purdue University Indianapolis (IUPUI) / In this dissertation, a beyond-CMOS approach to Static Random Access Memory (SRAM) design is investigated using exploratory transistors including Tunnel Field Effect Transistor (TFET), Carbon Nanotube Field Effect Transistor (CNFET) and Graphene NanoRibbon Field Effect Transistor (GNRFET). A Figure-of-Merit (FOM) based comparison of 6-transistor (6T) and a modified 8-transistor (8T) single-port SRAMs designed using exploratory devices, and contemporary devices such as a FinFET and a CMOS process, highlighted the performance benefits of GNRFETs and power benefits of TFETs. The results obtained from the this work show that GNRFET-based SRAM have very high performance with a worst-case memory access time of 27.7 ps for a 16x4-bit 4-word array of 256-bitcells. CNFET-based SRAM bitcell consume the lowest average power during read/write simulations at 3.84 uW, while TFET-based SRAM bitcell show the best overall average and static power consumption at 4.79 uW and 57.8 pW respectively. A comparison of these exploratory devices with FinFET and planar CMOS showed that FinFET-based SRAM bitcell consumed the lowest static power at 39.8 pW and CMOS-based SRAM had the best read, write and hold static noise margins at 201 mV, 438 mV and 413 mV respectively. Further, the modification of 8T-SRAMs via dual wordlines for individually controlling read and write operations for uni-directional transistors TFET and CNFET show improvement in read static noise margin (RSNM). In dual wordline CNFET 8T-SRAM, an RSNM improvement of approximately 23.6x from 6 mV to 142 mV was observed by suppressing the read wordline (RWL) from a nominal supply of 0.71 V down to 0.61 V. In dual wordline TFET 8T-SRAM, an RSNM improvement of approximately 16.2x from 5 mV to 81 mV was observed by suppressing the RWL from a nominal supply of 0.6 V down to 0.3 V. Next, the dissertation explores whether the robustness of SRAM arrays can be improved. Specifically, the robustness related to noise margin during the write operation was investigated by implementing a negative bitline (NBL) voltage scheme. NBL improves the write static noise margin (WSNM) of the SRAM bitcells in the row of the array to which the data is written during a write operation. However, this may cause degraded hold static noise margin (HSNM) of un-accessed cells in the array. Applying a negative wordline voltage (NWL) on un-accessed cells during NBL shows that the NWL can counter the degraded HSNM of un-accessed cells due to NBL. The scheme, titled as NBLWL, also allows the supply of a lower NBL, resulting in higher WSNM and write-ability benefits of accessed row. By applying a complementary negative wordline voltage to counter the half-select condition in columns, the WSNM of cells in accessed rows was boosted by 10.9% when compared to a work where no negative bitline was applied. In addition, the HSNM of un-accessed cells remain the same as in the case where no negative bitline was implemented. Essentially, a 10.9% boost in WSNM without any degradation of HSNM in un-accessed cells is observed. The dissertation also focuses on the impact of process-related variations in SRAM arrays to correlate and characterize silicon data to simulation data. This can help designers remove pessimistic margins that are placed on critical signals to account for expected process variation. Removing these pessimistic margins on critical data paths that dictate the memory access time results in performance benefits for the SRAM array. This is achieved via an in-situ silicon monitor titled SRAM process and ageing sensor (SPAS), which can be used for silicon and ageing characterization, and silicon debug. The SPAS scheme is based on a process variation tolerant technique called RAZOR that compares the data arriving on the output of the sense amplifiers during the read operation. This scheme can estimate the impact of process variation and ageing induced slow-down on critical path during read operation of an array with high accuracy. The estimation accuracy in a commercially available 65nm CMOS technology for a 16x16 array at TT, and global SS and FF corners at nominal supply and testing temperature were found to be 99.2%, 94.9% and 96.5% respectively. Finally, redundant columns, an architectural-level scheme for tolerating failing SRAM bitcells in arrays without compromising performance and yield, is studied. Redundant columns are extra columns that are programmed when bitcells in the regular columns of an array are slower or have higher leakage than expected post-silicon. The regular columns are often permanently disabled and remain unused for the chip lifetime once redundant columns are enabled. In the SRRC scheme proposed in this thesis, the regular columns are only temporarily disabled, and re-used at a later time in chip life cycle once the previously awakened redundant columns become slower than the disabled regular columns. Essentially, the scheme can identify and temporarily disable the slowest column in an array until other mitigating factors slow down active columns. This allows the array to operate at a memory access time closer to the target access time regardless of other mitigating factors slowing down bitcells in arrays during chip life cycle. An approximate 76.4% reduction in memory access time was observed from a 16x16 array from simulations in a commercially available 65nm CMOS technology with respect to a work where no redundancy was employed.

With the development of powerful computational resources such as Digital Signal Processors and Field Programmable Gate Arrays, It has become possible to utilize many radio functions via software. This is the main concept of an up-and-coming technology of Software Defined Radio. In the Thesis, a number of platforms for implementation of Software Defined Radio has been evaluated. Platform that proved to be most suitable for the project was Ettus’ USRP N210. Using the platform, implementation of 802.15.4 Zigbee’s physical layer was done, where experiments whose outputs can later be used to compare performance with respect to "hardware radios" were performed. / Med utvecklingen av enheter med kraftfulla beräkningsegenskaper som “Digital Signal Processors” och “Field Programmable Gate Arrays” har det blivit möjligt att implementera flera radiofunktioner i mjukvara. Det är huvudkonceptet i den uppåtgående teknologin mjukvaru definierad radio.I det här examensarbetet har ett flertal plattformar för mjukvaru definierad radioutvärderats. Plattformen som visade sig vara mest lämplig för projektet var Ettus USRP N210. En implementation av IEEE 802.15.4 Zigbees fysiska lager har realiserats till plattformen. Experiment, vars utdata senare kan användas för att jämföra prestanda mellan mjukvaru definierad radio och hårdvaru baserad radio, har även utförts. / TESLA - Time-critical and Safe wireLess Automation communication / GAUSS - Guaranteed Automation communication Under Severe disturbanceS

This work is concerned with the implementation and implication of non-volatile charge storage on VLSI system design. To that end, the floating-gate pFET (fg-pFET) is considered in the context of large-scale arrays. The programming of the element in an efficient and predictable way is essential to the implementation of these systems, and is thus explored. The overhead of the control circuitry for the fg-pFET, a key scalability issue, is examined. A light-weight, trend-accurate model is absolutely necessary for VLSI system design and simulation, and is also provided. Finally, several reconfigurable and reprogrammable systems that were built are discussed.

When computational resources are limited, especially multipliers, distributed arithmetic (DA) is used in lieu of the typical multiplier-based filtering structures. However, DA is not well suited for adaptive applications. The bottleneck is updating the memory table. Several attempts have been done to accelerate updating the memory, but at the expense of additional memory usage and of convergence speed. To develop an adaptive DA filter with an uncompromised convergence rate, the memory table must be fully updated. In this research, an efficient method for fully updating a DA memory table is proposed. The proposed update method is based on exploiting the temporal locality of the stored data and subexpression sharing. The proposed update method reduces the computational workload and requires no additional memory resources. DA using the proposed update method is called conjugate distributed arithmetic. Filters can also be constructed from analog components. Often, for lower precision computations, analog circuits use less power and less chip area than their digital counterparts. However, digital components are often used because of their ease of reprogrammability. Achieving such reprogrammability in analog is possible, but at the expense of additional chip area. A reprogrammable mixed-signal DA finite impulse response (FIR) filter is proposed to address the issues with reprogrammable analog FIR filters that are constructing compact reprogrammable filtering structures, non-symmetric and imprecise filter coefficients, inconsistent sampling of the input data, and input sample data corruption. These issues are successfully addressed using distributed arithmetic, digital registers, and epots. Also, a mixed-signal DA second-order section (SOS), which is used as the building block for higher order infinite impulse response filters, was proposed. The type of issues with an analog SOS filter are similar to those of an analog FIR filter, which are the lack of a compact reprogrammable filtering structure, the imprecise filter coefficients, the inconsistent sampling of the data, and the corruption of the data samples. These issues are successfully addressed using distributed arithmetic and digital registers.

O programa CBERS é uma parceria entre o governo Brasileiro e o governo Chinês para desenvolvimento de satélites para sensoriamento remoto. A metodologia proposta será aplicada na Câmera Multi Espectral (MUXCAM) dos satélites CBERS-3 e 4, a primeira deste gênero a ser totalmente produzida no Brasil. Devido à alta confiabilidade exigida, principalmente devido ao custo elevado, as aplicações aeroespaciais que envolvem hardware reconfigurável devem possuir uma metodologia de desenvolvimento, desde a definição dos requisitos até o processo de verificação e validação. A utilização da linguagem VHDL e da ferramenta de síntese, processo este chamado de metodologia clássica, produzem um circuito final não otimizado, eliminando redundâncias e alterando a arquitetura proposta. Este trabalho propõe uma metodologia que busca garantir a utilização de uma única arquitetura desde o início do ciclo de desenvolvimento até sua finalização. Esta metodologia torna o processo de desenvolvimento mais confiável e determinístico. / The CBERS program is a partnership between Brazil and China to produce satellites for remote sensing, producing images of the Earth for studies in several areas, mainly the ones related to the sustainable exploitation of natural resourses. The methodology proposed in this work will be applied on the satellite CBERS-3 e 4\'s Multispectral Camera (MUXCAM), the first of its gender fully produced in Brazil. Because the high reliability involved in aerospace applications, a methodology is necessary from software specification until the verification and validation process to guarantee the high reliability. The use of the synthesis tool and VHDL produce a poor circuit, eliminating redundance and making architectural changes. This work proposes a methodology to keep the architectural the same all development cycle, make the development process more trustful for aerospace applications.

O programa CBERS é uma parceria entre o governo Brasileiro e o governo Chinês para desenvolvimento de satélites para sensoriamento remoto. A metodologia proposta será aplicada na Câmera Multi Espectral (MUXCAM) dos satélites CBERS-3 e 4, a primeira deste gênero a ser totalmente produzida no Brasil. Devido à alta confiabilidade exigida, principalmente devido ao custo elevado, as aplicações aeroespaciais que envolvem hardware reconfigurável devem possuir uma metodologia de desenvolvimento, desde a definição dos requisitos até o processo de verificação e validação. A utilização da linguagem VHDL e da ferramenta de síntese, processo este chamado de metodologia clássica, produzem um circuito final não otimizado, eliminando redundâncias e alterando a arquitetura proposta. Este trabalho propõe uma metodologia que busca garantir a utilização de uma única arquitetura desde o início do ciclo de desenvolvimento até sua finalização. Esta metodologia torna o processo de desenvolvimento mais confiável e determinístico. / The CBERS program is a partnership between Brazil and China to produce satellites for remote sensing, producing images of the Earth for studies in several areas, mainly the ones related to the sustainable exploitation of natural resourses. The methodology proposed in this work will be applied on the satellite CBERS-3 e 4\'s Multispectral Camera (MUXCAM), the first of its gender fully produced in Brazil. Because the high reliability involved in aerospace applications, a methodology is necessary from software specification until the verification and validation process to guarantee the high reliability. The use of the synthesis tool and VHDL produce a poor circuit, eliminating redundance and making architectural changes. This work proposes a methodology to keep the architectural the same all development cycle, make the development process more trustful for aerospace applications.