Power amplifiers are an indispensible part of the wireless communication systems. Conventional PAs provide peak efficiency at peak output power which is obtained at a certain fixed optimum resistance. These kind of amplifiers are normally called switched-mode power amplifiers (SMPAs) and are used for constant envelope signals. However, there is low efficiency at low output power which is the linear operation of a PA and is used for the amplification of non-constant envelope signals. For an optimum PA design, linearity and efficiency are the requirements. There are efficiency  enhancement techniques and Doherty architecture is one such approach. Classical Doherty (symmetric) approach entertains the signals that have peak to average power ratio (PAPR) of 6 dB. Applications like Long Term Evolution (LTE) having high PAPR of nearly 9 dB demand efficiency throughout the back-off range. Therefore the challenge is to design and implement an asymmetric Doherty power amplifier that ensures high efficiency in the back-off range greater than 6 dB. This work presents the design and implementation of an Asymmetric Doherty Power Amplifier (ADPA) for 12 dB back-off at 2.65 GHz in Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs) technology. The carrier and peaking amplifiers are biased in class-B and C mode of operations, respectively. A branchline coupler is used to divide the input signal equally to amplifiers input. A 10 W GaN HEMT transistor is used as an active device for both amplifiers. The design has been implemented with ideal transmission lines and then shifted to microstrip lines using 508 um substrate. The measurement results of the ADPA prototype, when drain of carrier and peaking devices are biased at 24 V and 28 V  respectively, showed an input power back of (IPBO) of 9.68 dB with almost same power added efficiency (PAE) of 44% throughout the entire back-off range. The simulations are done with Agilent ADS and Momentum is used for Electromagnetic (EM) simulation.

With the growth of smart phones, the demand for more broadband, data centric technologies are being driven higher. As mobile operators worldwide plan and deploy 4th generation (4G) networks such as LTE to support the relentless growth in mobile data demand, the need for strategically positioned pico-sized cellular base stations known as ‘pico-cells’ are gaining traction. In addition to having to design a transceiver in a much compact footprint, pico-cells must still face the technical challenges presented by the new 4G systems, such as reduced power consumptions and linear amplification of the signals. The RF power amplifier (PA) that amplifies the output signals of 4G pico-cell systems face challenges to minimize size, achieve high average efficiencies and broader bandwidths while maintaining linearity and operating at higher frequencies. 4G standards as LTE use non-constant envelope modulation techniques with high peak to average ratios. Power amplifiers implemented in such applications are forced to operate at a backed off region from saturation. Therefore, in order to reduce power consumption, a design of a high efficiency PA that can maintain the efficiency for a wider range of radio frequency signals is required. The primary focus of this thesis is to enhance the efficiency of a compact RF amplifier suitable for a 4G pico-cell base station. For this aim, an integrated two way Doherty amplifier design in a compact 10mm x 11.5mm monolithic microwave integrated circuit using GaN device technology is presented. Using non-linear GaN HFETs models, the design achieves high effi-ciencies of over 50% at both back-off and peak power regions without compromising on the stringent linearity requirements of 4G LTE standards. This demonstrates a 17% increase in power added efficiency at 6 dB back off from peak power compared to conventional Class AB amplifier performance. Performance optimization techniques to select between high efficiency and high linearity operation are also presented. Overall, this thesis demonstrates the feasibility of an integrated HFET Doherty amplifier for LTE band 7 which entails the frequencies from 2.62-2.69GHz. The realization of the layout and various issues related to the PA design is discussed and attempted to be solved.

With the growth of smart phones, the demand for more broadband, data centric technologies are being driven higher. As mobile operators worldwide plan and deploy 4th generation (4G) networks such as LTE to support the relentless growth in mobile data demand, the need for strategically positioned pico-sized cellular base stations known as ‘pico-cells’ are gaining traction. In addition to having to design a transceiver in a much compact footprint, pico-cells must still face the technical challenges presented by the new 4G systems, such as reduced power consumptions and linear amplification of the signals. The RF power amplifier (PA) that amplifies the output signals of 4G pico-cell systems face challenges to minimize size, achieve high average efficiencies and broader bandwidths while maintaining linearity and operating at higher frequencies. 4G standards as LTE use non-constant envelope modulation techniques with high peak to average ratios. Power amplifiers implemented in such applications are forced to operate at a backed off region from saturation. Therefore, in order to reduce power consumption, a design of a high efficiency PA that can maintain the efficiency for a wider range of radio frequency signals is required. The primary focus of this thesis is to enhance the efficiency of a compact RF amplifier suitable for a 4G pico-cell base station. For this aim, an integrated two way Doherty amplifier design in a compact 10mm x 11.5mm monolithic microwave integrated circuit using GaN device technology is presented. Using non-linear GaN HFETs models, the design achieves high effi-ciencies of over 50% at both back-off and peak power regions without compromising on the stringent linearity requirements of 4G LTE standards. This demonstrates a 17% increase in power added efficiency at 6 dB back off from peak power compared to conventional Class AB amplifier performance. Performance optimization techniques to select between high efficiency and high linearity operation are also presented. Overall, this thesis demonstrates the feasibility of an integrated HFET Doherty amplifier for LTE band 7 which entails the frequencies from 2.62-2.69GHz. The realization of the layout and various issues related to the PA design is discussed and attempted to be solved.

With the growth of smart phones, the demand for more broadband, data centric technologies are being driven higher. As mobile operators worldwide plan and deploy 4th generation (4G) networks such as LTE to support the relentless growth in mobile data demand, the need for strategically positioned pico-sized cellular base stations known as ‘pico-cells’ are gaining traction. In addition to having to design a transceiver in a much compact footprint, pico-cells must still face the technical challenges presented by the new 4G systems, such as reduced power consumptions and linear amplification of the signals. The RF power amplifier (PA) that amplifies the output signals of 4G pico-cell systems face challenges to minimize size, achieve high average efficiencies and broader bandwidths while maintaining linearity and operating at higher frequencies. 4G standards as LTE use non-constant envelope modulation techniques with high peak to average ratios. Power amplifiers implemented in such applications are forced to operate at a backed off region from saturation. Therefore, in order to reduce power consumption, a design of a high efficiency PA that can maintain the efficiency for a wider range of radio frequency signals is required. The primary focus of this thesis is to enhance the efficiency of a compact RF amplifier suitable for a 4G pico-cell base station. For this aim, an integrated two way Doherty amplifier design in a compact 10mm x 11.5mm monolithic microwave integrated circuit using GaN device technology is presented. Using non-linear GaN HFETs models, the design achieves high effi-ciencies of over 50% at both back-off and peak power regions without compromising on the stringent linearity requirements of 4G LTE standards. This demonstrates a 17% increase in power added efficiency at 6 dB back off from peak power compared to conventional Class AB amplifier performance. Performance optimization techniques to select between high efficiency and high linearity operation are also presented. Overall, this thesis demonstrates the feasibility of an integrated HFET Doherty amplifier for LTE band 7 which entails the frequencies from 2.62-2.69GHz. The realization of the layout and various issues related to the PA design is discussed and attempted to be solved.

The power amplifiers are typically the most power-consuming block in wireless communication systems. Spectrum is expensive, and newer technologies demand transmission of maximum amount of data with minimum spectrum usage. This requires sophisticated modulation techniques, leading to wide, dynamic signals that require linear amplification. Although linear amplification is achievable, it always comes at the expense of efficiency. Most of the modern wireless applications such as WCDMA use non-constant envelope modulation techniques with a high peak to average ratio. Linearity being a critical issue, power amplifiers implemented in such applications are forced to operate at a backed off region from saturation. Therefore, in order to overcome the battery lifetime limitation, a design of a high efficiency power amplifier that can maintain the efficiency for a wider range of radio frequency input signal is the obvious solution. A new technique that improves the drain efficiency of a linear power amplifier such as Class A or AB, for a wider range of output power, has been investigated in this research. The Doherty technique consists of two amplifiers in parallel; in such a way that the combination enhances the power added efficiency of the main amplifier at 6dB back off from the maximum output power. The classes of operation of power amplifier (A, AB, B, C etc), and the design techniques are presented. Design of a 2.14 GHz Doherty power amplifier has been provided in chapter 4. This technique shows a 15% increase in power added efficiency at 6 dB back off from the compression point. This PA can be implemented in WCDMA base station transmitter. / Master of Science

Les signaux des nouveaux standard de communications (LTE) ont une grande différence entre la puissance maximale et moyenne (PAPR), cela n'est pas favorable pour l'utilisation dans les amplificateurs conventionnels vu qu'ils présentent un rendement maximale seulement quand ils travaillent au niveau de puissance maximale. Des amplificateurs de puissance Doherty pour présenter une efficacité constante pour une large gamme de puissance constituent une solution favorable à ce problème. Ce travail présente la méthodologie de conception et des résultats de mesure d'un amplificateur de puissance Doherty entièrement intégré dans la technologie 65 nm CMOS avec une constante PAE sur un 7 dB de plage de puissance. Mesures de 2,4 GHz à 2,6 GHz montrent des performances constantes PAE à partir du niveau de 20% jusqu'à 24% avec une puissance de sortie maximale de 23,4 dBm. Le circuit a été conçu avec une attention particulière pour le faible coût. / The signals of the new communication standards (LTE) show a great difference between the peak and its average power (PAPR) being unsuitable for use with conventional power amplifiers because they present maximum efficiency only when working with maximum power. Doherty power amplifiers for presenting a constant efficiency for a wide power range represent a favorable solution to this problem. This work presents the design methodology and measurements results of a fully integrated Doherty Power Amplifier in 65 nm CMOS technology with constant PAE over a 7 dB backoff. Measurements from 2.4 GHz to 2.6 GHz show constant PAE performance starting in 20% level up to 24% with a maximum output power of 23.4 dBm.The circuit was designed with special attention to low cost.

abstract: The continuing advancement of modulation standards with newer generations of cellular technology, promises ever increasing data rate and bandwidth efficiency. However, these modulation schemes present high peak to average power ratio (PAPR) even after applying crest factor reduction. Being the most power-hungry component in the radio frequency (RF) transmitter, power amplifiers (PA) for infrastructure applications, need to operate efficiently at the presence of these high PAPR signals while maintaining reasonable linearity performance which could be improved by moderate digital pre-distortion (DPD) techniques. This strict requirement of operating efficiently at average power level while being capable of delivering the peak power, made the load modulated PAs such as Doherty PA, Outphasing PA, various Envelope Tracking PAs, Polar transmitters and most recently the load modulated balanced PA, the prime candidates for such application. However, due to its simpler architecture and ability to deliver RF power efficiently with good linearity performance has made Doherty PA (DPA) the most popular solution and has been deployed almost exclusively for wireless infrastructure application all over the world. Although DPAs has been very successful at amplifying the high PAPR signals, most recent advancements in cellular technology has opted for higher PAPR based signals at wider bandwidth. This lead to increased research and development work to innovate advanced Doherty architectures which are more efficient at back-off (BO) power levels compared to traditional DPAs. In this dissertation, three such advanced Doherty architectures and/or techniques are proposed to achieve high efficiency at further BO power level compared to traditional architecture using symmetrical devices for carrier and peaking PAs. Gallium Nitride (GaN) based high-electron-mobility (HEMT) technology has been used to design and fabricate the DPAs to validate the proposed advanced techniques for higher efficiency with good linearity performance at BO power levels. / Dissertation/Thesis / Doctoral Dissertation Electrical Engineering 2018

abstract: This thesis is a study of Bandwidth limitation of basestation power amplifier and its Doherty application. Fundamentally, bandwidth of a power amplifier (PA) is limited by both its input and output prematch networks and its Doherty architecture, specifically the impedance inverter between the main and auxiliary amplifier. In this study, only the output prematch network and the Doherty architecture follows are being investigated. A new proposed impedance inverter in the Doherty architecture exhibits an extended bandwidth compared to traditional quarterwave line. Base on the loadline analysis, output impedance of the power amplifier can be represented by a loadline resistor and an output shunt capacitor. Base on this simple model, the maximum allowed bandwidth of the output impedance of the power amplifier can be estimated using the Bode-Fano method. However, since power amplifier is in fact nonlinear, harmonic balance simulation is used to loadpull the device across a broad range of frequencies. Base on the simulated large signal impedance at maximum power, the prematch circuitry can be designed. On a system level, the prematch power amplifier is used in Doherty amplifier. Two different prematch circuitries, T- section and shunt L methods are investigated along with their comparison in the Doherty architecture at both back off power and peak power condition. The last section of the thesis will be incorporating the proposed impedance inverter structure between the main and auxiliary amplifiers. The simulated results showed the shunt L prematch topology has the least impedance dispersion across frequency. Along with the new impedance inverter structure, the 65% efficiency bandwidth improves by 50% compared to the original impedance inverter structure at back off power level. / Dissertation/Thesis / Masters Thesis Electrical Engineering 2014

Yes / This work develops a novel dynamic load modulation Power Amplifier (PA) circuity that can provide an optimum compromise between linearity and efficiency while covering multiple cellular frequency bands. Exploiting monolithic microwave integrated circuits (MMIC) technology, a fully integrated 1W Doherty PA architecture is proposed based on 0.1 µm AlGaAs/InGaAs Depletion- Mode (D-Mode) technology provided by the WIN Semiconductors foundry. The proposed wideband DPA incorporates the harmonic tuning Class-J mode of operation, which aims to engineer the voltage waveform via second harmonic capacitive load termination. Moreover, the applied post-matching technique not only reduces the impedance transformation ratio of the conventional DPA, but also restores its proper load modulation. The simulation results indicate that the monolithic drive load modulation PA at 4 V operation voltage delivers 44% PAE at the maximum output power of 30 dBm at the 1 dB compression point, and 34% power-added efficiency (PAE) at 6 dB power back-off (PBO). A power gain flatness of around 14 ± 0.5 dB was achieved over the frequency band of 23 GHz to 27 GHz. The compact MMIC load modulation technique developed for the 5G mobile handset occupies the die area of 3.2. / This research was funded by the European Regional Development Fund (FEDER), through COMPETE 2020, POR ALGARVE 2020, Fundação para a Ciência e a Tecnologia (FCT) under i-Five Project (POCI-01-0145-FEDER-030500). This work is also part of the POSITION-II project funded by the ECSEL joint Undertaking under grant number Ecsel-345 7831132-Postitio-II-2017-IA. This work is supported by FCT/MCTES through national funds and when applicable co-funded EU funds under the project UIDB/50008/2020-UIDP/50008/2020. The authors would like to thank the WIN Semiconductors foundry for providing the MMIC GaAs pHEMT PDKs and technical support. This work is supported by the Project TEC2017-88242-C3-2-R- Spanish Ministerio de Ciencia, Innovación e Universidades and EU-FEDER funding.

This thesis presents an optimized drive signal control system for a 2.5 GHz Doherty power amplifier (PA). The designed system enables independent control of the amplitudes and phases of the drive signals fed to the inputs of two parallel PAs. This control system is demonstrated here for Doherty PA architecture with a combiner network which is used as an impedance inversion between the path of two parallel connected PAs. Independent control of the inputs is achieved by incorporating a variable attenuator (VA) and a variable phase shifter (VPS) in each of the two parallel paths. Integrating VA and VPS allows driving varying power levels with an arbitrary phase difference between the individual parallel PAs. A Combiner network consists of a quarter-wave transmission line at the output of the main power amplifier, which is used to invert the impedance between the main and peaking transistor. The specific VA (Qorvo QPC6614) and VPS (Qorvo QPC2108) components that are used for the test system provide an amplitude attenuation range from 0.5 dB to 31.5 dB with a step size of 0.5 dB and a phase range from 0◦ to 360◦ for a step size of 5.6◦at the intended operating frequency of 2.5 GHz, offering the benefit of characterizing the behavior of PAs under test for an extensive range of drive signals to optimize the output performance such as power added efficiency (PAE) or adjacent channel leakage ratio (ACLR). For demonstration, the designed drive signal control system is integrated with two parallel GaN transistor-based PAs (Qorvo QPD0005) with a P1dB of 37.7 dBm. Each PA is preceded by a drive amplifier with a gain of 17.8 dB to boost the power fed into the PA. The control system incorporates various custom-designed components such as a 20 dB directional coupler, a 3 dB Wilkinson power splitter, a quarter-wave transmission line, and a Doherty power combiner. While Qorvo QPD0005 (DUT) is used as a specific test case in this demonstration, the proposed system can characterize the behavior of a wide range of Doherty PAs.