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Microelectronic systems such as cell phones, computers, consumer electronics, and implantable medical devices consist of subsystems which in turn consist of other subsystems and components. When such systems are designed, fabricated, assembled, and tested, they need to meet reliability, cost, performance, and other targets for being competitive. The design of reliable electronic packaging systems in a systematic and timely manner requires a consistent and unified method for allocating, predicting, and assessing reliability and for recommending design changes at the component and system level with consideration of both random and wearout failures. Accordingly, this dissertation presents a new unified knowledge modeling method for System Design for Reliability (SDfR) called the Reliability Object Model (ROM) method. The ROM method consistently addresses both reliability allocation and assessment for systems composed of series and parallel subsystems. The effectiveness of the ROM method has been demonstrated for allocating, predicting, and assessing reliability, and the results show that ROM is more effective compared to existing methods, providing richer semantics, unified techniques, and improved SDfR quality. Furthermore, this dissertation develops representative reliability metrics for random and wearout failures, and incorporates such metrics into ROM together with representative algorithms for allocation, assessment, and design change recommendations. Finally, this research implemented the ROM method in a computing framework and demonstrated its applicability using several relevant microelectronic system test cases and prototype SDfR tools.

Thesis--Auburn University, 2009. / Abstract. Includes bibliographical references (p. 111-121).

Thesis--Auburn University, 2009. / Abstract. Includes bibliographical references (p. 170-177).

In mobile and handheld consumer electronic markets, product use conditions drive the requirement for mechanical strength and device durability. The majority of relatively large form factor electronic components in a laptop, mobile internet device, PDA, or mobile phone use an adhesive as a stiffener to help protect the component from physical stresses imposed by daily wear and tear. Described herein is an innovative solution referred to as Solid State Pre-Formed Electronics Adhesive (SPEA), which enables a decrease in circuit board manufacturing throughput time while increasing mechanical durability with a consistent and characterized adhesive application process. Today, many consumer electronic ODM's (Original Design Manufacturers) and CM's (Contract Manufacturers) use a liquid adhesive dispensed after placement of an electronic component within the SMT (Surface Mount Technology) process. On average, this adds up to 60 seconds to the throughput time of a typical motherboard as the material needs to be applied and then cured. In addition, the current adhesive dispense application process is not tightly controlled and is highly variable depending on operator, material type, and circuit board density. Data will demonstrate that the effect of the adhesive deposition profile and consistency in application directly affects repeatable margin increase gains in a dynamic stress event. In partnership with a specialty chemical company, a unique thermoset epoxy compound was designed to provide maximum component to circuit board interconnect strength while maintaining its form at ambient temperatures. When applied to electronics manufacturing, the compound has the following advantages over current solutions: 1. Reduced Manufacturing Processing Time: Enables a solution that can be transitioned transparently into a circuit board manufacturing facility which reduces the average processing time for a typical device motherboard. 2. Improved Application Repeatability: Enables a solution that increases adhesive deposition consistency and placement repeatability, critical in achieving improved dynamic performance. 3. Delivers a Reference, Characterized Solution: Current industry adhesive application techniques and materials vary widely and component manufacturers cannot validate reliability performance with a confident baseline. This is due to the high variability of performance in commercially available adhesives. SPEA provides a characterized adhesive solution with a clear baseline margin increase on which to evaluate dynamically stressed system performance. The need to continually increase the resistance to component damage through dynamic testing is a critical aspect to consider given market trends and device roadmaps. Large component manufacturers have the opportunity to further embed themselves into untapped markets where portability and performance converge and drive the need for more robust packaging solutions. The development and application of SPEA will continue to maintain silicon and packaging reliability as consumer devices continue to shrink, becoming ever more portable.

Approved for public release; distribution is unlimited / Solder joints provide both electrical and mechanical interconnections between a silicon chip and the packaging substrate in an electronic application. The thermomechanical cycling (TMC) in the solder due to the mismatch of the coefficient of thermal expansion (CTE) between the silicon chip and the substrate causes numerous reliability challenges. This situation is aggravated by the ongoing transition to lead-free solders worldwide, and the trend towards larger, hotter-running chips. Therefore, improved solder joints, with higher resistance to creep and low-cycle fatigue, are necessary for future generations of microelectronics. This study reports in the development a process to fabricate solder joints with a fine distribution of shape memory alloys (SMA) NiTi particulates. The microstructure and interface zone of the as-reflowed solder-SMA composite has been characterized. / Lieutenant, United States Navy

by Chow Yeung Ming = 化學鍍鎳層的表面性質與焊接能力之關係 / 周洋明. / Thesis (M.Phil.)--Chinese University of Hong Kong, 2000. / Includes bibliographical references (leaves 62-65). / Text in English; abstracts in English and Chinese. / by Chow Yeung Ming = Hua xue du nie ceng de biao mian xing zhi yu han jie neng li zhi guan xi / Zhou Yangming. / Abstract --- p.i / 論文摘要 --- p.ii / Acknowledgements --- p.iii / Table of Contents --- p.v / List of Figures --- p.viii / List of Tables --- p.ix / Abbreviations --- p.x / Chapter Chapter 1 --- INTRODUCTION / Chapter 1.1 --- Electroless Plating (Autocatalytic Deposition) --- p.1 / Chapter 1.2 --- Electroless Nickel (EN) Plating --- p.2 / Chapter 1.3 --- Types of Electroless Nickel Deposits --- p.2 / Chapter 1.4 --- Properties of Electroless Nickel --- p.5 / Chapter 1.5 --- Applications of Electroless Nickel in Electronic Packaging Industry --- p.7 / Chapter 1.6 --- Importance of Solderability --- p.8 / Chapter 1.7 --- Literature Review of Solderability Studies of Electroless Nickel --- p.9 / Chapter 1.8 --- Motivations & Aims of Studies --- p.10 / Chapter Chapter 2 --- EXPERIMENTAL & INSTRUMENTATION / Chapter 2.1 --- Electroless Nickel Plating --- p.11 / Chapter 2.2 --- Solderability Measurements / Chapter 2.2.1 --- Soldering --- p.13 / Chapter 2.2.2 --- Various test methods for solderability --- p.13 / Chapter 2.2.3 --- Wetting balance method --- p.15 / Chapter 2.2.4 --- Solderability measurements of electroless nickel deposits --- p.17 / Chapter 2.2.5 --- Assessment of wetting curves --- p.19 / Chapter 2.3 --- Surface Oxidation Studies / Chapter 2.3.1 --- Use of X-ray photoelectron spectroscopy (XPS) in surface characterization --- p.19 / Chapter 2.3.2 --- XPS system --- p.22 / Chapter 2.3.3 --- Surface composition of electroless nickel deposits --- p.22 / Chapter 2.3.4 --- Oxide thickness characterization by angle-resolved XPS --- p.25 / Chapter 2.3.5 --- Oxide thickness characterization by XPS depth profiling with low-energy-ion sputtering --- p.28 / Chapter 2.4 --- Surface Morphology Studies / Chapter 2.4.1 --- Surface morphology studies by scanning Auger electron microscopy (SAM) & atomic force microscopy (AFM) --- p.28 / Chapter 2.4.2 --- SAM studies of electroless nickel surfaces --- p.29 / Chapter 2.4.3 --- AFM studies of electroless nickel surfaces --- p.29 / Chapter 2.5 --- Oxide Quality Studies --- p.31 / Chapter Chapter 3 --- RESULTS & DISCUSSIONS / Chapter 3.1 --- Solderability Measurements by the Wetting Balance Method --- p.33 / Chapter 3.2 --- Surface Oxidation Studies / Chapter 3.2.1 --- Surface composition of electroless nickel deposits --- p.36 / Chapter 3.2.2 --- Oxide thickness characterization by angle-resolved XPS --- p.38 / Chapter 3.2.3 --- Oxide thickness characterization by XPS depth profiling with low-energy-ion sputtering --- p.44 / Chapter 3.2.4 --- Conclusion --- p.47 / Chapter 3.3 --- Surface Morphology Studies / Chapter 3.3.1 --- SAM studies of electroless nickel surfaces --- p.49 / Chapter 3.3.2 --- AFM studies of electroless nickel surface --- p.49 / Chapter 3.3.3 --- Conclusion --- p.53 / Chapter 3.4 --- Interpretation of Wetting Kinetics of Electroless Nickel --- p.54 / Chapter Chapter 4 --- CONCLUSIONS & FURTHER STUDIES / Chapter 4.1 --- Conclusions --- p.59 / Chapter 4.2 --- Further Studies --- p.60 / Appendix --- p.61 / References --- p.62

Thesis (M.S.)--State University of New York at Binghamton, Thomas J. Watson School of Engineering and Applied Sciences, Systems Science and Industrial Engineering Department, 2006. / Includes bibliographical references.

Thesis (M.S.)--State University of New York at Binghamton, Department of Systems Science and Industrial Engineering, 2006. / Includes bibliographical references.

Thesis (M.S.)--State University of New York at Binghamton, Mechanical Engineering Department, 2006. / Includes bibliographical references.