In today’s world the multi-standard wireless receivers are gaining more and more popularity. End-users want to access voice, data and streaming media from a single wireless terminal. An ideal approach for multi-standard receiver front-end is to digitize a wide band RF signal available from the antenna. All radio functions such as downconversion, demodulation and channel selection can be then performed in the digital domain. Analog to Digital Converter in such a case should guarantee very high linearity, speed and bandwidth specifications while consuming a lot of power. Unfortunately an ADC with such stringent requirements cannot be realized in today’s CMOS technology. In a typical receiver a mixer is used to downconvert the RF signal to baseband (or IF) before digitization is performed. A passive mixer is often used in this case to mitigate the effect of the low frequency flicker noise. Specially it can be a sampling mixer which also serves as a S/H circuit usually required for A/D conversion. In this thesis a lowpass sigma-delta converter with RF sampling is presented. The ΣΔ modulator is SC passive circuit plus comparator, so an operational amplifier usually needed to realize the integrator is avoided. To reduce the complexity, the sampling mixer in front of the modulator is merged with the passive loop filter. As a result the sampling mixer is closed in the modulator loop, so the overall linearity of the frontend is improved to some extent. Downconversion is combined with digitization that reduces the circuit complexity as well.The challenges while digitizing high frequency RF signal are discussed in details. Switches required to realize the loop filter are very critical and tend to be nonlinear. Parasitic effects associated with MOS transistors strongly show up at GHz frequencies. Optimized transistor sizes are obtained through simulation while addressing the speed and linearity trade-off. Another major challenge is the kT/C noise that is the real bottleneck in high frequency SC circuit design. A thermal noise model for ΣΔ-modulator with second-order loop filter is presented and it is shown that a passive ΣΔ-modulator is  in fact thermal noise limited rather than quantization noise limited. It is because the capacitor values are limited by the very high sampling frequency used in this case.The downconverting lowpass ΣΔ modulator with second order SC passive loop filter and 1-bit quantizer is simulated at transistor level in 90nm CMOS process. This modulator can operate at very high sampling frequency upto 4GHz and can sample RF signal with carrier of upto 4GHz as well. The designed ΣΔ modulator is flexible and supports sub-sampling by 2 to 8 (fs = 500MHz, ... 2GHz). Besides, the presented design is very power efficient as it does not use OpAmps – which consume most of the power in the typical ΣΔ modulators. From schematic simulation on average, signal-to-noise and distortion ratio (SNDR) of 52 dB is obtained (ENOB = 8.3). SNDR results does not vary much for three different cases of baseband digitalization, RF sampling and RF sub-sampling. This SNDR value seems to be a good number for a passive sigma-delta modulator. The detailed simulation results for the three cases discussed in the thesis work shown that, the modulator performs equally well for a wide range of sampling and RF signal frequencies.

A wave digital filter is derived from an analog filter, which is realized as classical doubly resistively terminated reactancefilters. Perfectly designed wave digital filters express good dynamic signal range, low roundoff noise and excellent stabilitycharacteristics with respect to nonlinearity which are produced due to finite wordlength effects. Wave digital filters inheritthe sensitivity properties from analog filters, therefore, coefficients values can be selected to favorable values.Wave digital filters, derived from ladder filters, have low coefficient sensitivity in the passband and stopband. These WDFsare very complicated and are non-modular. The lattice wave digital filters are modular and are not complex. However, theyhave very high sensitivity in the stopband and thus require large coefficient wordlengths. The number of coefficients equalsthe filter order which have to be odd.This thesis discusses the wave digital filter structures that are modular because they are designed by cascading the first-orderand second-order sections. These WDFs can be pipelined. They also exhibit all the above mentioned favorable properties.Similar to lattice WDFs, these structures are restricted to symmetrical and antisymmetrical transfer functions. The synthesisof these structures is based on the factorization of the scattering matrix of lossless two-ports.In this thesis work, lowpass wave digital filters based on circulator-tree structure are designed with different orders startingfrom 3 and going upto 13. In parallel to these circulator-tree wave digital filters, the simple digital filters are also designedwith the same specification. The results of the two filters are compared with each other. It is observed that impulse responseand attenuation response of the two kind of filters perfectly match. Therefore, it is can be concluded that circulator-tree WDFupto Nth order can be synthesized. The implementation examples of two filter with order 3 and order 7 is presented in thisdocumentation for ready reference. It has also been shown that the order of sections does not affect the transfer function ofthe filter. Noise has been introduced and adaptor sections are penetrated. From the results it is concluded that the order of theadaptor sections does not matter and also that the noise does not affect the other adaptors sections, it only propagates throughother adaptors sections.

Large scale path loss modeling plays a fundamental role in designing both fixed and mobile radio systems. Predicting the radio coverage area of a system is not done in a standard manner. Wireless systems are expensive systems. Therefore, before setting up a system one has to choose a proper method depending on the channel environment, frequency band and the desired radio coverage range. Path loss prediction plays a crucial role in link budget analysis and in the cell coverage prediction of mobile radio systems. Especially in urban areas, increasing numbers of subscribers brings forth the need for more base stations and channels. To obtain high efficiency from the frequency reuse concept in modern cellular systems one has to eliminate the interference at the cell boundaries. Determining the cell size properly is done by using an accurate path loss prediction method. Starting from the radio propagation phenomena and basic path loss models this thesis aims at describing various accurate path loss prediction methods used both in rural and urban environments. The Walfisch-Bertoni and Hata models, which are both used for UHF propagation in urban areas, were chosen for a detailed comparison. The comparison shows that the Walfisch-Bertoni model, which involves more parameters, agrees with the Hata model for the overall path loss.

The goal of the thesis is to design the star-based mesh topology by introducing multiple pan-coordinators (hub/switches) under a multipath-fading environment and to improve the data transaction rate of a network which usually gets worst when there is a single pan-coordinator for synchronization of devices in conventional mesh topology; also reduce the hop-count as least as possible. Most of the work has been done on NS-2 network simulator; therefore the research model which has been used here is a simulation model. Altogether 3 simulations have been done. The first scenario is done on a simplest mesh network with a single coordinator and a radio propagation model which has been used is two-ray ground reflection model. The second scenario simulation is similar to the first scenario but in-order to provide multi-path signal fading and highly congested environment the propagation model which has been used this time is shadowing model. The final simulation which has been done is of multiple-star based mesh topology it also uses the similar radio propagation model which has been defined for second scenario. An intensive performance measurement of all the three simulations has been done in terms of transactions made per-second, packet drop rate along with an analysis of packet drop. An hop-count is also measured between star and mesh topology. For multiple star based mesh topology it can be assumed if multiple stars with a routing capability can be used then nodes in a network will be synchronized or re-synchronized with least number of hops in the congested network with a near-by pan-coordinator (hub/switch). One of the major applications of this topology can be automobile manufacturing industry where alot of machines are installed in a congested network and monitoring of every area is mandatory for swift production.

At Acreo AB located in Norrköping, Sweden, research and development in the field of organic electronics have been conducted since 1998. Several electronic devices and systems have been realized. In late 2003 a commercial printing press was installed to test large scale production of these devices. Prior to the summer of 2005 the project made significant progress. As a step towards industrialisation, the variability and yield of the printing process needed to bee studied. A decision to implement Statistical Process Control (SPC) and Design of Experiments (DOE) to evaluate and improve the process was taken. SPC has been implemented on the EC-patterning step in the process. A total of 26 Samples were taken during the period October-December 2005. An - and s-chart were constructed from these samples. The charts clearly show that the process is not in statistical control. Investigations of what causes the variation in the process have been performed. The following root causes to variation has been found: PEDOT:PSS-substrate sheet resistance and poorly cleaned screen printing drums. After removing points affected by root causes, the process is still not in control. Further investigations are needed to get the process in control. Examples of where to go next is presented in the report. In the DOE part a four factor full factorial experiment was performed. The goal with the experiment was to find how different factors affects switch time and life length of an electrochromic display. The four factors investigated were: Electrolyte, Additive, Web speed and Encapsulation. All statistical analysis was performed using Minitab 14. The analysis of measurements from one day and seven days after printing showed that: - Changing Electrolyte from E230 to E235 has small effect on the switch time - Adding additives Add1 and Add2 decreases the switch time after 1 and 7 days - Increasing web speed decreases the switch time after 1 and 7 days - Encapsulation before UV-step decreases the switch time after 7 days

<p>During the past years has the Nostrum Network on Chip <i>(NoC)</i> been developed to become a competitive platform for network based on-chip communication. The Nostrum NoC provides a versatile communication platform to connect a large number of intellectual properties <i>(IP) </i>on a single chip. The communication is based on a packet switched network which aims for a small physical footprint while still providing a low communication overhead. To reduce the communication network size, a queue-less network has been the research focus. This network uses de ective hot-potato routing which is implemented to perform routing decisions in a single clock cycle.</p><p>Using a platform like this results in increased design reusability, validated signal integrity, and well developed test strategies, in contrast to a fully customised designs which can have a more optimal communication structure but has a significantly longer development cycle to verify the new design accordingly.</p><p>Several factors are considered when designing a communication platform. The goal is to create a platform which provides low communication latency, high throughput, low power consumption, small footprint, and low design, verification, and test overhead. Proximity Congestion Awareness is one technique that serves to reduce</p><p>the network load. This leads to that the latency is reduced which also increases the network throughput. Another technique is to implement low latency paths called<i> Data Motorways</i> achieved through a clocking method called Globally Pseudochronous Locally Synchronous clocking. Furthermore, virtual circuits can be used to provide guarantees on latency and throughput. Such guarantees are dificult in</p><p>hot-potato networks since network access has to be ensured. A technique that implements virtual circuits use looped containers that are circulating on a predefined circuit. Several overlapping virtual circuits are possible by allocating the virtual circuits in different Temporally Disjoint Networks.</p><p>This thesis summarise the impact the presented techniques and methods have on the characteristics on the Nostrum model. It is possible to reduce the network load by a factor of 20 which reduces the communication latency. This is done by distributing load information between the Switches in the network. Data Motorways</p><p>can reduce the communication latency with up to 50% in heavily loaded networks. Such latency reduction results in freed buffer space in the Switch registers which allows the traffic rate to be increased with about 30%.</p>

<p>Large scale path loss modeling plays a fundamental role in designing both fixed and mobile radio systems. Predicting the radio coverage area of a system is not done in a standard manner. Wireless systems are expensive systems. Therefore, before setting up a system one has to choose a proper method depending on the channel environment, frequency band and the desired radio coverage range. Path loss prediction plays a crucial role in link budget analysis and in the cell coverage prediction of mobile radio systems. Especially in urban areas, increasing numbers of subscribers brings forth the need for more base stations and channels. To obtain high efficiency from the frequency reuse concept in modern cellular systems one has to eliminate the interference at the cell boundaries. Determining the cell size properly is done by using an accurate path loss prediction method. Starting from the radio propagation phenomena and basic path loss models this thesis aims at describing various accurate path loss prediction methods used both in rural and urban environments. The Walfisch-Bertoni and Hata models, which are both used for UHF propagation in urban areas, were chosen for a detailed comparison. The comparison shows that the Walfisch-Bertoni model, which involves more parameters, agrees with the Hata model for the overall path loss.</p>

The main focus of this thesis is placed on high frequency PCB signal Integrity Is-sues and RF/Microwave filters using EBG structures. From the signal Integrity aspect, two topics were mainly discussed. On one hand, the effect of increasing frequency on classical design rules for crosstalk reduction in PCBs was investigated experimentally and by full-wave simulations. An emphasis was placed on the 3×W spacing rule and the use of guard traces. Single-ended and differential transmission lines were considered. S-parameter measurements and simu-lations were carried out at high-frequency (up to 20 GHz). The results emphasize the necessity to reevaluate traditional design rules for their suitability in high frequency applications. Also, the impacts of using guard traces for high frequency crosstalk re-duction were clearly pointed out. On the other hand, the effect of high loss PCB ma-terials on the signal transmission characteristics of microstrip lines at high frequency (up to 20 GHz) was treated. Comparative studies were carried out on different micro-strip configurations using standard FR4 substrate and a high frequency dielectric ma-terial from Rogers, Corporation. The experimental results highlight the dramatic im-pact of high dielectric loss materials (FR4 and solder mask) and magnetic plating metal (nickel) on the high frequency signal attenuation and loss of microstrip trans-mission lines. Besides, the epoxy-based SU8 photoresist was characterized at high frequency (up to 50 GHz) using on-wafer conductor-backed coplanar waveguide transmission lines. A relative dielectric constant of 3.2 was obtained at 30 GHz. Some issues related to the processing of this material, such as cracks, hard-skin, etc, were also discussed. Regarding RF/Microwave filters, the concept of Electromagnetic Band Gap (EBG) was used to design and fabricate novel microstrip bandstop filters using periodically modified substrate. The proposed EBG structures, which don’t suffer conductor backing issues, exhibit interesting frequency response characteristics. The limitations of modeling and simulation tools in terms of speed and accuracy are also examined in this thesis. Experiments and simulations were carried out show-ing the inadequacies of the Spice diode model for the simulations in power electronics. Also, an Artificial Neural Network (ANN) model was proposed as an alternative and a complement to full-wave solvers, for a quick and sufficiently accurate simulation of interconnects. A software implementation of this model using Matlab’s ANN toolbox was shown to considerably reduce (by over 800 times) the simulation time of microstrip lines using full-wave solvers such as Ansoft’s HFSS and CST’s MWS. Finally, a novel cooling structure using a double heatsink for high performance electronics was presented. Methods for optimizing this structure were also discussed. / QC 20100809

<p>This thesis considers the problem of making dynamic models for industrial processes by combining physical modelling with experimental data. The focus is on distributed parameter systems, that is, systems for which the model structure involves partial differential equations (PDE). Distributed parameter systems are important in many applications, e.g., in chemical process systems and in intracellular biochemical processes, and involve for instance all forms of transport and transfer phenomena. For such systems, the postulated model structure usually requires a finite dimensional approximation to enable identification and validation using experimental data. The finite dimensional approximation involves translating the PDE model into a set of ordinary differential equations, and is termed model reduction.</p><p>The objective of the thesis is two-fold. First, general PDE model reduction methods which are efficient in terms of model order for a given level of accuracy are studied. The focus here is on a class of methods called moving mesh methods, in which the discretization mesh is considered a dynamic degree of freedom that can be used for reducing the model reduction error. These methods are potentially highly efficient for model reduction of PDEs, but often suffer from stability and robustness problems. In this thesis it is shown that moving mesh methods can be cast as standard feedback control problems. Existing moving mesh methods are analyzed based on tools and results available from control theory, and plausible explanations to the robustness problems and parametric sensitivity experienced with these methods are provided. Possible remedies to these problems are also proposed. A novel moving finite element method, Orthogonal Collocation on Moving Finite Elements (OCMFE), is proposed based on a simple estimate of the model reduction error combined with a low order linear feedback controller. The method is demonstrated to be robust, and hence puts only small demands on the user.</p><p>In the second part of the thesis, the integration of PDE model reduction methods with grey-box modelling tools available for finite dimensional models is considered. First, it is shown that the standard approach based on performing model reduction using some ad hoc discretization method and model order, prior to calibrating and validating the reduced model, has a number of potential pitfalls and can easily lead to falsely validated PDE models. To overcome these problems, a systematic approach based on separating model reduction errors from discrepancies between postulated model structures and measurement data is proposed. The proposed approach is successfully demonstrated on a challenging chromatography process, used for separation in biochemical production, for which it is shown that data collected at the boundaries of the process can be used to clearly distinguish between two model structures commonly used for this process.</p>

Les futurs calculateurs de haute performance (HPC) devront faire face à deux défis majeurs : la densité de la bande passante d'interconnexion et les problématiques de consommation d'énergie. La photonique silicium est aujourd’hui perçue comme une solution solide pour aborder ces questions, tant du fait de ses performances que de sa viabilité économique en raison de sa compatibilité directe avec la microélectronique CMOS. Actuellement, une tendance de fond conduit à remplacer les interconnexions métalliques par des liens optiques ; cette évolution a été initiée sur des liaisons grandes distances mais atteint actuellement le niveau des liaisons entre cartes électroniques et pourrait conduire à moyen terme à l’intégration de liens optiques au sein mêmes des circuits intégrés électroniques. La prochaine étape est en effet envisagée pour l'interconnexion des processeurs au sein de puces multi-cœurs en positionnant les liens photoniques sur un même support de silicium (« interposer »). Plusieurs travaux ont démontré la possibilité d'intégrer tous les éléments nécessaires pour la réalisation de liaisons optiques sur un substrat de silicium ouvrant des perspectives de co-intégration optique et électronique très riches.Dans ce contexte, la première contribution de cette thèse est l'optimisation d'un lien de photonique de silicium en terme d'efficacité énergétique par bit (à minimiser). L'optimisation que nous avons conduite a pris en compte une modélisation de la consommation d'énergie pour le laser de la liaison, celle de l’étape dé-sérialisation des données, du résonateur en anneau considéré comme modulateur optique et des circuits de réception (« front-end ») et de décision. Les résultats ont montré que les principales contributions à la consommation de puissance au sein d’un lien optique sont la puissance consommée par le laser et les circuits d’alimentation du modulateur électro-optique. En considérant des paramètres de consommation extraits de simulations numériques et de travaux publiés dans des publications récentes, le débit optimal identifié se trouve dans la plage comprise entre 8 Gbits/seconde et 22 Gbits/seconde selon le nœud technologique CMOS utilisé (65nm à 28nm FD SOI). Il est également apparu qu’une diminution de la consommation de puissance statique du modulateur utilisé pourrait encore ramener ce débit optimal en-dessous de 8 Gbits/seconde.Afin de vérifier ces résultats, un circuit intégré récepteur de liaison optique a été conçu et fabriqué en se basant sur un débit de fonctionnement de 8 Gbits/seconde. Le récepteur utilise une technique d’entrelacement temporel destinée à réduire la vitesse d'horloge nécessaire et à éviter potentiellement l’étape de dé-sérialisation dédiée des informations. / Future high performance computer (HPC) systems will face two major challenges: interconnection bandwidth density and power consumption. Silicon photonic technology has been proposed recently as a cost-effective solution to tackle these issues. Currently, copper interconnections are replaced by optical links at rack and board level in HPCs and data centers. The next step is the interconnection of multi-core processors, which are placed in the same package on silicon interposers, and define the basic building blocks of these computers. Several works have demonstrated the possibility of integrating all elements needed for the realization of short optical links on a silicon substrate.The first contribution of this thesis is the optimization of a silicon photonic link for highest energy efficiency in terms of energy per bit. The optimization provides energy consumption models for the laser, a de- and serialization stage, a ring resonator as modulator and supporting circuitry, a receiver front-end and a decision stage. The optimization shows that the main consumers in optical links is the power consumed by the laser and the modulator's supporting circuitry. Using consumption parameters either gathered by design and simulation or found in recent publications, the optimal bit rate is found in the range between 8 Gbps and 22 Gbps, depending on the used CMOS technology. Nevertheless, if the static power consumption of modulators is reduced it could decrease even below 8 Gbps.To apply the results from the optimization an optical link receiver was designed and fabricated. It is designed to run at a bit rate of 8 Gbps. The receiver uses time interleaving to reduce the needed clock speed and aleviate the need of a dedicated deserialization stage. The front-end was adapted for a wide dynamic input range. In order to take advantage of it, a fast mechanism is proposed to find the optimal threshold voltage to distinguish ones from zeros.Furthermore, optical clock channels are explored. Using silicon photonics a clock can be distributed to several processors with very low skew. This opens the possibility to clock all chips synchronously, relaxing the requirements for buffers that are needed within the communication channels. The thesis contributes to this research direction by presenting two novel optical clock receivers. Clock distribution inside chips is a major power consumer, with small adaptation the clock receivers could also be used inside on-chip clocking trees.