Embedded systems, including critical embedded systems (CES) are increasingly present in the modern society, providing specific solutions from small to large complex systems, such as in cars, airplanes, and healthcare equipment. Failures in these systems can result in damage to human beings, and to the environment, or can represent an unrecoverable financial loss. In this sense, it is very important to ensure they are built with quality. To provide such quality, it is necessary to consider their software architecture, which impacts on the quality of the systems. This way, the main objective of this Masters project is to propose a quality model concerning the most important quality attributes for CES, which may be used to support (but not limited to) architectural activities such as analysis and evaluation in the context of CES. / Sistemas embarcados, incluindo sistemas embarcados críticos (SEC), estão cada vez mais presentes na sociedade moderna, provendo soluções específicas que variam de sistemas pequenos até sistemas grandes e complexos, como é possível encontrar em carros, aviões e equipamentos médicos. Falhas nesses sistemas podem resultar em danos à seres humanos e ao meio ambiente, ou então em uma perda financeira irrecuperável. Sendo assim, é muito importante garantir que os SEC sejam construídos e apresentem um nível adequado de qualidade. Para garantir que esses sistemas alcancem tal qualidade, é necessário considerar sua arquitetura de software, já que esta impacta de maneira significativa na qualidade do software enquanto artefato ou produto. Deste modo, o objetivo deste projeto de mestrado é de propor um modelo de qualidade que contém os atributos de qualidade mais importantes para SEC, servindo como artefato para apoiar a execução de atividades arquiteturais (além de outras que possam se beneficiar) tais como análise e avaliação, no contexto de SEC.

Notre objectif est de proposer une méthodologie pour le développement d'un intergiciel embarqué dans l'automobile offrant des services de communication aux applications. Le cadre d'utilisation de nos travaux est la conception de systèmes embarqués dans les véhicules. Ces applications requièrent un intergiciel capable de fournir des services standards de communication, qui cachent la localisation des participants aux échanges, qui masquent l'hétérogénéité des plates-formes de communication, et qui garantissent le respect des contraintes temporelles imposées sur l'échanges et sur l'exécution des participants. La méthodologie proposée vise la conception d'un intergiciel optimisé et pour cela aborde deux aspects : la spécification d'une architecture d'implémentation, et la construction d'une configuration faisable. L'architecture d'implémentation est optimisée dans le sens où l'intergiciel est adapté à l'environnement d'exécution (le système d'exploitation OSEK/VDX OS), et minimise son utilisation des ressources disponibles. Elle apporte une réponse, d'une part, au niveau de la spécification d'une architecture logicielle (construite à l'aide de design patterns ), et, d'autre part, à la manière dont cette architecture est déployée sur une plate-forme concrète (sous la forme d'un ensemble de tâches). La procédure proposée pour la construction de la configuration de l'intergiciel calcule les caractéristiques temporelles faisables de l'intergiciel et des trames émises par les stations d'un réseau CAN. Elle prévoit aussi une étape pour le calcul d'une allocation de priorités faisable pour les tâches de l'application sur chaque station. L'optimalité de la configuration est atteinte en assurant le respect de toutes les contraintes temporelles imposées sur les échanges et sur l'exécution des tâches de l'application et de l'intergiciel. / Our objective is to propose a methodology for the development of an automotive embedded middleware that provides communication services to the applicative level software. This work is focused on the design of automotive functions, where the nowadays context demands a middleware capable of offering standard communication services, hiding the localization of the participants in the exchanges, masking the heterogeneity of communication platforms, and ensuring that the timing constraints imposed on the exchanges and on the execution of the participants are met. The proposed methodology is aimed for the design of an optimised middleware. For this purpose, it deals with two topics: the specification of an implementation architecture, and the construction of a feasible configuration. The implementation architecture is optimised because the middleware is well adapted to its execution environment (operating system OSEK/VDX OS), and minimizes the utilization of the available resources. It contributes, on the one hand, to a specification of a software architecture (built using design patterns), and, on the other hand, to mechanisms allowing to deploy this software architecture onto a concrete platform (under the form of a set of tasks). The algorithm proposed for the construction of a configuration determines feasible timing characteristics for the middleware and for the frames exchanged over a CAN bus. It covers also the calculation of a feasible set of priorities for the applicative tasks executing on each station of the bus. The correctness of the configuration is achieved by ensuring that the timing constraints imposed on the exchanges and on the execution of the applicative and middleware tasks are met.

Durant la dernière décennie, la miniaturisation des technologies de semi-conducteurs et de l’intégration à grande échelle a donné lieu à la conception de systèmes complexes, notamment l’intégration de plusieurs milliards de transistors sur un même die. Cette tendance pose de nombreux défis de fabrication et de fiabilité tels que la dissipation de puissance, la variabilité technologique et la polyvalence des applications. Les problèmes de fiabilité, représentées par la présence de points chauds thermiques peuvent accélérer la dégradation des transistors, et par conséquent réduire la durée de vie des puces, également appelée "vieillissement". Afin de relever ces défis, de nouvelles solutions sont nécessaires, basées notamment sur des systèmes auto-adaptatifs. Ces systèmes sont principalement composées d’une boucle de contrôle avec trois processus : (i) la surveillance, qui est chargée d’observer l’état du système, (ii) la prise de décision, qui analyse les informations collectées et prend des décisions pour optimiser le comportement du système et (iii) l’action qui ajuste les paramètres du système en conséquence. Cependant, une adaptation dépendre de façon critique sur le processus de suivi qui devrait fournir une estimation précise sur l’état du système de façon rentable. Dans cette thèse, nous étudions d’abord le suivi de la consommation d’énergie. Nous développons une méthode basée sur plusieurs algorithmes de fouille de données "data mining", pour surveiller l’activité de commutation sur quelques signaux pertinents sélectionnés au niveau RTL. La méthode proposée se compose d’un flot générique qui peut être utilisé pour modéliser la consommation d’énergie pour n’importe quel circuit RTL sur n’importe quelle technologie. Deuxièmement, nous améliorons le flot proposé pour estimer le comportement thermique globale de puce et de développer une nouvelle technique de placement des capteurs thermique sur puce. Les algorithmes proposés choisissent systématiquement le meilleur compromis entre la précision de l’observation et le coût représenté par le nombre de capteurs intégrés sur puce. La surface de la puce est décomposée en plusieurs zones thermiquement homogènes.Outre la partie conception, les systèmes embarqués modernes intègrent des capteurs matériels (analogiques ou numériques) qui peuvent être utilisés pour surveiller l’état du système. Ces méthodes industrielles sont généralement très coûteuses et nécessitent un grand nombre d’unités pour produire des informations précises avec une résolution à grain fin. Une solution alternative pour fournir une estimation précise de l’état du système est réalisée avec un ensemble de compteurs de performance qui peut être configuré pour effectuer le suivi des événements logiques à différents niveaux. Dans ce cas, nous proposons un nouvel algorithme pour la sélection des événements performance pertinents à partir des ressources locales, partagées et système. Nous proposons ensuite une implémentation d'un algorithme d'estimation basé sur un réseau neuronal. La méthode proposée est robuste contre les variations de température extérieure. En outre, estimation thermique est aussi peut être réalisé en utilisant les événements logiques actuelles et historiques, et la précision est évaluée sur la base de la profondeur dans le passé.Enfin, une fois la méthode de suivi et la cible définies et le système est configuré, la méthode de surveillance doit être utilisée au moment de "Run-time". Nous avons mis en place une boucle d’adaptation complète, avec un suivi dynamique de l’état du système afin atteindre une meilleure efficacité énergétique. / Over the last decade, the miniaturization of semiconductor technologies and the large-scale integration has given rise to complex system design, including the integration of several billions of transistors on a single die. This trend poses many manufacturing and reliability challenges such as power dissipation, technological variability and application versatility. The reliability issues represented by the presence of thermal hotspots can accelerate the degradation of the transistors, and consequently reduce the chip lifetime, also referred to as “aging”. In order to address these challenges, new solutions are required, based in particular on self-adaptive systems. Such systems are mainly composed of a control loop with three processes: (i) the monitoring, which is responsible for observing the state of the system, (ii) the diagnosis, which analyzes the information collected and makes decisions to optimize the behavior of the system, and (iii) the action that adjusts the system parameters accordingly. However, effective adaptations depend critically on the monitoring process that should provide an accurate estimation about the system state in a cost-effective manner. In this thesis, we firstly investigate the monitoring of the power consumption. We develop a method, based on several data mining algorithm, to monitor the toggling activity on a few relevant signals selected at the RTL level. The proposed method consists of a generic flow that can be used to model the power consumption for any RTL circuit on any technology. Secondly, we improve the proposed flow by estimating the overall chip thermal behavior and developing a new technique of on-die thermal sensor placement. The proposed algorithms systematically choose the best trade-off between accuracy and overhead. The surface of the chip is decomposed into several thermally homogeneous regions.Besides the design part, modern embedded systems integrates hardware sensors (analog or digital) that can be used to monitor the system’s state. These industrial methods are usually very expensive, and require a large number of units to produce precise information at a fine-grained resolution. An alternative solution to provide an accurate estimation of system’s state is achieved with a set of performance counters that can be configured to track logical events at different levels. To this end, we propose a novel algorithm for the selection of the relevant performance events from the local, shared and system resources. We propose then an implementation of a neural network based estimation algorithm. The proposed method is robust against the external temperature variations. Furthermore, thermal estimation is also can be achieved using the current and historic logical events, and the accuracy is evaluated on the basis of the depth in the past.Finally, once the tracking method and target are defined and the system is configured, the monitoring method should be used at “Run-time”. We implemented a complete adaptation loop, with a dynamic monitoring of the system’s state in order to achieve better energy efficiency.

<div>In autonomous driving, medical diagnosis, unmanned vehicles and many other new technologies, the neural network and computer vision has become extremely popular and influential. In particular, for classifying objects, convolutional neural networks (CNN) is very efficient and accurate. One version is the Region-based CNN (RCNN). This is our selected network design for a new implementation in an FPGA.</div><div><br></div><div>This network identies stop signs in an image. We successfully designed and trained an RCNN network in MATLAB and implemented it in the hardware to use in an embedded real-world application. The hardware implementation has been achieved with maximum FPGA utilization of 220 18k_BRAMS, 92 DSP48Es, 8156 FFS, 11010 LUTs with an on-chip power consumption of 2.235 Watts. The execution speed in FPGA is 0.31 ms vs. the MATLAB execution of 153 ms (on computer) and 46 ms (on GPU).</div>

O consumo de energia é uma das questões mais importantes em sistemas embarcados. Estudos demonstram que neste tipo de sistema a cache é responsável por consumir a maior parte da energia fornecida ao processador. Na maioria dos processadores embarcados, os parâmetros de configuração da cache são fixos e não permitem mudanças após sua fabricação/síntese. Entretanto, este não é o cenário ideal, pois a configuração da cache pode não ser adequada para uma determinada aplicação, tendo como consequência menor desempenho na execução e consumo excessivo de energia. Neste contexto, este trabalho apresenta uma implementação em hardware, utilizando computação reconfigurável, capaz de reconfigurar automática, dinâmica e transparentemente a quantidade de ways e por consequência o tamanho da cache de dados do processador embarcado LEON3, de forma que a cache se adeque à aplicação em tempo de execução. Com esta técnica, espera-se melhorar o desempenho das aplicações e reduzir o consumo de energia do sistema. Os resultados dos experimentos demonstram que é possível reduzir em até 5% o consumo de energia das aplicações com degradação de apenas 0.1% de desempenho / Energy consumption is one of the most important issues in embedded systems. Studies have shown that in this type of system the cache consumes most of the power supplied to the processor. In most embedded processors, the cache configuration parameters are fixed and do not allow changes after manufacture/synthesis. However, this is not the ideal scenario, since the configuration of the cache may not be suitable for a particular application, resulting in lower performance and excessive energy consumption. In this context, this project proposes a hardware implementation, using reconfigurable computing, able to reconfigure the parameters of the LEON3 processor\'s cache in run-time improving applications performance and reducing the power consumption of the system. The result of the experiment shows it is possible to reduce the processor\'s power consumption up to 5% with only 0.1% degradation in performance

Este trabalho apresenta o projeto e arquitetura de uma plataforma para execução de Agentes com funções implementadas em hardware, tomando vantagem do uso de hardware reconfigurável. Os Agentes em hardware são implementados utilizando dispositivos FPGA (Field-programmable Gate Array). O trabalho estende trabalhos anteriores semelhantes na área, com o diferencial de adicionar suporte às funcionalidades de reconfiguração parcial do hardware, suportar aplicações que demandam alto desempenho em hardware – como processamento de sinais e imagens – e redução de recursos de hardware necessários para execução da interface em software. A plataforma proposta utiliza o framework JADE (Java Agent Development Framework), que é um dos frameworks mais populares no estado da arte de desenvolvimento de Agentes e compatível com outros frameworks de Agentes através da conformidade aos padrões FIPA (Foundation for Intelligent Physical Agents). Com o uso do JADE, a plataforma possibilita a comunicação entre Agentes com funções implementadas em hardware e Agentes puramente implementados em software dentro de um mesmo SMA (Sistema Multi-Agente). Uma funcionalidade notável do JADE é a possibilidade de migração de Agentes entre plataformas de um mesmo SMA. Através do uso da reconfiguração parcial de hardware em conjunto com o JADE, a plataforma permite a migração de Agentes de software para hardware e vice-versa, além de suportar reconfiguração de múltiplos Agentes em hardware com um único FPGA. A plataforma faz uso de um único chip através do uso de um processador soft core implementado na lógica programável. O uso deste processador é um diferencial neste trabalho, e mostra que é possível utilizar o JADE em sistemas embarcados com recursos de processamento limitados. Ou seja, em um Agente cuja principal função é implementada em hardware, basta um processador bastante simples para atuar como uma interface entre o hardware e o framework de Agentes. O uso do processador dentro do FPGA tem também o benefício de oferecer formas de acesso mais integrado ao hardware, permitindo maior desempenho na transmissão de dados ao hardware. A plataforma foi validada através de estudos de caso de Agentes com implementações em hardware e em software, incluindo um estudo de caso aplicado de processamento de imagem embarcado utilizando VANTs (Veículos Aéreos Não-Tripulados). O estudo também apresenta comparações de desempenho entre a execução dos Agentes em hardware e em outras plataformas embarcadas de prateleira. Os experimentos realizados mostram um ganho significativo de desempenho nas implementações em FPGA, especialmente considerando processamento de imagens de alta resolução, mesmo considerando que o FPGA executa em frequências consideravelmente reduzidas em comparação às outras plataformas testadas. / This work described the design and architecture of a platform for execution of Agents whose functions are implemented in hardware, by leveraging the use of reconfigurable hardware. The hardware Agents are implemented using FPGA (Field-programmable Gate Array) devices. This work extends previous similar work in this field, while adding the features of hardware partial reconfiguration, supporting applications which require high performance in hardware – such as image or signal processing – and reducing the hardware resource for the software interface execution. The proposed platform makes use of the JADE (Java Agent Development Framework) framework, which is one of the most popular frameworks in state-of-the-art Agent development, and is also compatible with other Agent development frameworks due to compliance with FIPA (Foundation for Intelligent Physical Agents) standards. With the use of JADE, the platform enables communication among Agents which are implemented in hardware and Agents purely implemented in software, inside the same MAS (Multi-Agent System). One notable feature of JADE is the possibility of migrating Agents among platforms inside a single MAS. Through the use of hardware partial reconfiguration along with JADE, the platform enables the migration of Agents from software to hardware and viceversa, in addition to supporting múltiple hardware Agents in a single FPGA. The platform makes use of a single chip, by using a MicroBlaze soft core processor implemented in programmable logic. The use of this processor is a distinction on this work, and it shows that it is possible to use JADE on embedded systems with limited processing power. That is, in an Agent whose main function is implemented in hardware, a very simple processor to act as an interface between hardware and the Agent framework is enough. The use of the soft core processor inside the FPGA also has the benefit of offering more integrated ways of accessing hardware, enabling higher performance for transferring data to hardware. The platform was validated through case studies of hardware and software Agent implementation, including a case study applied to image processing using UAVs (Unmanned Aerial Vehicles). The study also shows performance comparisons between the Agent execution in hardware and in other off-the-shelf embedded platforms. The performed experiments report a significative performance increase in the FPGA implementations, particularly in high resolution image processing, even considering that the FPGA runs in considerably lower clock frequency than the other tested platforms.

During the last decades, improved sensor and hardware technologies as well as new methods and algorithms have made self-driving vehicles a realistic possibility in the near future. Thanks to this technology enhancement, many leading automotive and technology companies have turned their attention towards developing advanced driver assistance systems (ADAS) and self-driving vehicles. Autonomous vehicles are expected to have their first big impact in closed areas, such as mines, harbors and loading/offloading sites. In such areas, the legal requirements are less restrictive and the surrounding environment is more controlled and predictable compared to urban areas. Expected positive outcomes include increased productivity and safety, reduced emissions and the possibility to relieve the human from performing complex or dangerous tasks. Within these sites, different truck and trailer systems are used to transport materials. These systems are composed of several interconnected modules, and are thus large and highly unstable while reversing. This thesis addresses the problem of designing efficient motion planning and feedback control frameworks for such systems. First, a cascade controller for a reversing truck with a dolly-steered trailer is presented. The unstable modes of the system is stabilized around circular equilibrium configurations using a gain-scheduled linear quadratic (LQ) controller together with a higher-level pure pursuit controller to enable path following of piecewise linear reference paths. The cascade controller is then used within a rapidly-exploring random tree (RRT) framework and the complete motion planning and control framework is demonstrated on a small-scale test vehicle. Second, a path following controller for a reversing truck with a dolly-steered trailer is proposed for the case when the obtained motion plan is kinematically feasible. The control errors of the system are modeled in terms of their deviation from the nominal path and a stabilizing LQ controller with feedforward action is designed based on the linearization of the control error model. Stability of the closed-loop system is proven by combining global optimization, theory from linear differential inclusions and linear matrix inequality techniques. Third, a systematic framework is presented for analyzing stability of the closed-loop system consisting of a controlled vehicle and a feedback controller, executing a motion plan computed by a lattice planner. When this motion planner is considered, it is shown that the closed-loop system can be modeled as a nonlinear hybrid system. Based on this, a novel method is presented for analyzing the behavior of the tracking error, how to design the feedback controller and how to potentially impose constraints on the motion planner in order to guarantee that the tracking error is bounded and decays towards zero. Fourth, a complete motion planning and control solution for a truck with a dolly-steered trailer is presented. A lattice-based motion planner is proposed, where a novel parametrization of the vehicle’s state-space is proposed to improve online planning time. A time-symmetry result is established that enhance the numerical stability of the numerical optimal control solver used for generating the motion primitives. Moreover, a nonlinear observer for state estimation is developed which only utilizes information from sensors that are mounted on the truck, making the system independent of additional trailer sensors. The proposed framework is implemented on a full-scale truck with a dolly-steered trailer and results from a series of field experiments are presented.

Arbete på kandidatnivå som behandlar 3D skanning vid olika vinklar och de resultat de ger vid olika avstånd.

The integration between the computing world and the physical world in a single system is called Cyber-Physical Systems (CPS). CPS systems aim to improve understanding and influence in physical phenomena and environmental behaviors by computing means. The interaction of the computing world with the physical world, through the use of sensors, actuators and network communication often leads to the accomplishment of highly complex and multidisciplinary projects. Project management is a practice that enhances the success probability of a project, monitoring and controlling relevant aspects to the project execution. Project Management Body of Knowledge (PMBOK) is a set of best practices regarding project management which addresses ten knowledge areas aiming to support project managers from any application domain. Although PMBOK proposes a generic approach, some specialized practices for a particular application domain may benefit highly challenging projects. In this context, this research work aims to propose a set of best practices specific for CPS systems development projects. The proposed approach is called CPS-PMBOK (junction of terms cyber-physical systems and project management body of knowledge) and is based on PMBOK\'s three knowledge areas: scope, human resource and stakeholder. CPS-PMBOK includes: \\textit a CPS characterization model which supports the understanding of the system to be developed; and \\textit specializations of these three PMBOK\'s knowledge areas, which provide a whole new process for the project scope management as well as specific improvements of well-known techniques for both the human resource management and the stakeholders management. The goal of CPS-PMBOK is to enhance project effectiveness and CPS quality, embracing both project manager and developers. To evaluate CPS-PMBOK effectiveness and adherence, the practices were presented for project managers and developers in a R\\&D company. The practices: pre-elaborated list of requirements, specialized team division and technical trust showed as more relevant for each respective knowledge area, according to managers. For developers, the review requirements process, cross training and technical trust seems to contribute more for its respective knowledge areas / A integração entre o mundo computacional e o mundo físico em um único sistema é chamada de Sistemas Ciberfísicos (CPS - do inglês \"Cyber-Physical Systems\'\'). Sistemas CPS visam melhorar o entendimento e a influência nos fenômenos físicos por meios computacionais. A interação do mundo computacional com o mundo físico, por meio de sensores, atuadores e redes de comunicação, frequentemente leva à realização de projetos de alta complexidade e multidisciplinares. Gestão de projetos é uma prática que aumenta as chances de sucesso de um projeto, monitorando e controlando aspectos relevantes da realização do projeto. PMBOK (Project Management Body of Knowledge) é uma combinação de boas práticas relacionadas à gestão de projetos que trata dez áreas de conhecimento visando auxiliar gerentes de projeto de qualquer área de aplicação. Embora PMBOK proponha uma abordagem genérica, algumas práticas especializadas para determinadas áreas de aplicação particulares podem beneficiar projetos altamente desafiadores. Neste contexto, este projeto de pesquisa visa propor um conjunto de boas práticas para projetos de desenvolvimento de sistemas CPS. Essa abordagem é chamada de CPS-PMBOK (junção dos termos em inglês: cyber-physical systems e project management body of knowledge) e é baseada em três áreas de conhecimento do PMBOK: escopo, recursos humanos e partes interessadas. CPS-PMBOK inclui: (i) um modelo de caracterização de sistemas CPS que auxilia o entendimento do sistema a ser desenvolvido e (ii) especializações dessas três áreas de conhecimento do PMBOK, que fornecem um inteiramente novo processo para a gestão de escopo do projeto assim como melhorias específicas de técnicas conhecidas do PMBOK para os processos de gestão de recursos humanos e de gestão de partes interessadas. O objetivo da CPS-PMBOK é melhorar a eficácia do projeto e a qualidade do sistema CPS desenvolvido, abrangendo tanto o gerente de projeto quanto os desenvolvedores. Para avaliar a efetividade e aderência da CPS-PMBOK, as práticas foram apresentadas para gerentes de projeto e desenvolvedores em uma empresa de P&D. As práticas: listas pré-elaboradas de requisitos, divisão de equipes especializadas e confiança técnica mostraram-se mais relevantes para cada respectiva área do conhecimento, segundo os gerentes. Para os desenvolvedores, o processo de revisar requisitos, treinamento cruzado e confiança técnica pareceram contribuir mais para suas respectivas áreas do conhecimento

A demanda por novas tecnologias, melhoria de segurança e conforto para veículos urbanos cresceu consideravelmente nos últimos anos, motivando a indústria na criação de sistemas destinados ao apoio de motoristas (ADAS - Advanced Driver Assistance Systems). Este fato contribuiu para o desenvolvimento de diversos sistemas embarcados na área automobilística destacando-se, à prevenção de colisão a pedestres por veículos. Através do avanço em diversas pesquisas, começaram a circular pelas ruas veículos com sistemas anticolisão e com navegação autônoma. Contudo, para alcançar objetivos cada vez mais desafiadores, os projetistas precisam de ferramentas que permitam unir tecnologias e conhecimentos de áreas distintas de forma eficiente. Nesse contexto, há uma demanda para a construção de sistemas que aumentem o nível de abstração da modelagem de projetos para o processamento de imagens em sistemas embarcados e assim, possibilitando uma melhor exploração do espaço de projetos. A fim de contribuir para minimizar este problema, este trabalho de pesquisa demonstra o desenvolvimento de um framework para coprojeto de hardware e software específico para a construção de sistemas ADAS que utilizam visão computacional. O Framework visa facilitar o desenvolvimento dessas aplicações permitindo a exploração o espaço de projeto (DSE - Design Space Exploration), e assim contribuindo para um ganho de desempenho no desenvolvimento de sistemas embarcados quando comparados à construção totalmente de um modo manual. Uma das características deste projeto é a possibilidade da simulação da aplicação antes da síntese em um sistema reconfigurável. Os principais desafios deste sistema foram relacionados à construção do sistema de intercomunicação entre os diversos blocos de Propriedade Intelectual (IP) e os componentes de software, abstraindo do usuário final inúmeros detalhes de hardware, tais como gerenciamento de memória, interrupções, cache, tipos de dados (ponto flutuante, ponto fixo, inteiros) e etc, possibilitando um sistema mais amigável ao projetista. / The demand for new technologies, enhanced security and comfort for urban cars has grown considerably in recent years prompting the industry to create systems designed to support drivers (ADAS - Advanced Driver Assistance Systems). This fact contributed to the development of many embedded systems in the automotive area among them, the pedestrians collision avoidance. Through the advancement in various research, began circulating through the streets vehicles with anti-collision systems and autonomous navigation. However, to achieve ever more challenging goals, designers need tools to unite technology and expertise from different areas efficiently. In this context, there is a demand for building systems that increase the level of abstraction of models of image processing for use in embedded systems enabling better design space exploration. To help minimize this problem, this research demonstrates a develop a specific framework for hardware/software codesign to build ADAS systems using computer vision. The framework aims to facilitate the development of applications, allowing better explore the design space, and thus contribute to a performance gain in the development of embedded systems in relation to building entirely in hardware. One of the requirements of the project is the possibility of the simulation of an application before synthesis on a reconfigurable system. The main challenges of this system were related to the construction of the intercommunication system between the various Intellectual Property (IP) blocks and the software components, abstracting from the end user numerous hardware details, such as memory management, interruptions, cache, types (Floating point, fixed point, integers) and so on, enabling a more user-friendly system for the designer.