An accurate estimate of the mass of a passenger vehicle is important for several safety systems and environmental aspects. In this thesis, an algorithm for estimating the mass of a passenger vehicle using the recursive least squares methodis presented. The algorithm is based on a physical model of the vehicle and is designed to be able to run in real-time onboard a vehicle and uses the wheel torque signal calculated in the electrical control unit in the engine. Therefore no estimation of the powertrain is needed. This is one contribution that distinguishes this thesis from previous work on the same topic, which has used the engine torque. The benefit of this is that no estimation of the dynamics in the powertrain is needed. The drawback of using this method is that the algorithm is dependenton the accuracy of the estimation done in the engine electrical control unit. Two different versions of the recursive least squares method (RLS) have been developed - one with a single forgetting factor and one with two forgetting factors. The estimation performance of the two versions are compared on several different real-world driving scenarios, which include driving on country roads, highways, and city roads, and different loads in the vehicle. The algorithm with a single forgetting factor estimates the mass with an average error for all tests of 4.42% and the algorithm with multiple forgetting factors estimates the mass with an average error of 4.15 %, which is in line with state-of-the-art algorithms that are presented in other studies. In a sensitivity analysis, it is shown that the algorithms are robust to changes in the drag coefficient. The single forgetting factor algorithm is robust to changes in the rolling resistance coefficient whereas the multiple forgetting factor algorithm needs the rolling resistance coefficient to be estimated with fairly good accuracy. Both versions of the algorithm need to know the wheel radius with an accuracy of 90 %. The results show that the algorithms estimate the mass accurately for all three different driving scenarios and estimate highway roads best with an average error of 2.83 % and 2.69 % for the single forgetting factor algorithm and the multiple forgetting factor algorithm, respectively. The results indicate it is possible to use either algorithm in a real-world scenario, where the choice of which algorithm depends on sought-after robustness.

Title: Quantum computing algorithms for quantum chemistry Author: Jakub Višňák Abstract: The topic of this study is the simulation of the quantum algorithm for the diagonalization of the matrix representation of the all-electron Dirac-Coulomb hamiltonian of the SbH molecule. Two different limited CI expansions were used to describe both the ground state (X 0+ ) and the first excited doublet (A 1) by simulating the Iterative Phase Estinamtion Algorith (IPEA). In the simulations numerically performed in this work, the "compact mapping" has been employed for the representation of the evolution operator exp(i Hˆ t); in the theoretical part of the work, the "direct mapping" is described as well. The influence of the metodics for choosing the initial eigenvector estimate is studied in both IPEA A and IPEA B variants. For those variants, the success probabilities pm are computed for different single-points on the SbH dissociation curves. The initial eigenvector estimates based on the "CISD(2)" method are found to be sufficient for both studied LCI-expansions up to internuclear distance R  6 a0. The pm dependence on the overlap between the eigenvector in question and its inital estimate - 2 0  is studied the for IPEA B method. The usability of the both variants of the IPEA in possible later calculations is...

The goals for most of today’s receiver system are sampling at high-speed, with high resolution and with as few errors as possible. This master thesis describes the design of a high-speed sampling system with"state-of-the-art"components available on the market. The system is designed with a parallel Analog-to-digital converter (ADC) architecture, also called time interleaving. It aims to increase the sampling speed of the system. The system described in this report uses four 12-bits ADCs in parallel. Each ADC can sample at 125 MHz and the total sampling speed will then theoretically become 500 Ms/s. The system has been implemented and manufactured on a printed circuit board (PCB). Up to four boards can be connected in parallel to get 2 Gs/s theoretically. In an approach to increase the systems performance even further, a timing error estimation algorithm will be used on the sampled data. This algorithm estimates the timing errors that occur when sampling with non-uniform time interval between samples. After the estimations, the sampling clocks can be adjusted to correct the errors. This thesis is concerning some ADC theory, system design and PCB implementation. It also describes how to test and measure the system’s performance. No measurement results are presented in this thesis because measurements will be done after this project. The last part of the thesis discusses future improvementsto achieve even higher performance.

<p>The goals for most of today’s receiver system are sampling at high-speed, with high resolution and with as few errors as possible. This master thesis describes the design of a high-speed sampling system with"state-of-the-art"components available on the market. The system is designed with a parallel Analog-to-digital converter (ADC) architecture, also called time interleaving. It aims to increase the sampling speed of the system. The system described in this report uses four 12-bits ADCs in parallel. Each ADC can sample at 125 MHz and the total sampling speed will then theoretically become 500 Ms/s. The system has been implemented and manufactured on a printed circuit board (PCB). Up to four boards can be connected in parallel to get 2 Gs/s theoretically. </p><p>In an approach to increase the systems performance even further, a timing error estimation algorithm will be used on the sampled data. This algorithm estimates the timing errors that occur when sampling with non-uniform time interval between samples. After the estimations, the sampling clocks can be adjusted to correct the errors. </p><p>This thesis is concerning some ADC theory, system design and PCB implementation. It also describes how to test and measure the system’s performance. No measurement results are presented in this thesis because measurements will be done after this project. The last part of the thesis discusses future improvementsto achieve even higher performance.</p>