A millimeter-wave (W-Band) down-converter for Phased Focal Plane Arrays (PFPAs) has been designed and fabricated using the IBM Silicon-Germanium (SiGe) BiCMOS 8HP process technology. The radio frequency (RF) input range of the down-converter chip is from 70 95GHz. The intermediate frequency (IF) range is from 5 30GHz. The local oscillator (LO) frequency is fixed at 65GHz. The down-converter chip has been designed to achieve a conversion gain greater than 20dB, a noise figure (NF) below 10dB and input return loss greater than 10dB. The chip also has novel LO circuitry facilitating LO feed-through among down-converters chips in parallel. This wide bandwidth down-converter will be part of millimeter-wave PFPA receiver designed and fabricated in collaboration with the University of Massachusetts-Amherst Department of Astronomy. This PFPA receiver will be installed on Green Bank Telescope (GMT) / Large millimeter wave telescope (LMT) in Q2 of 2014. This project is collaboration between the University of Massachusetts-Amherst (UMass), Brigham Young University (BYU) and National Radio Astronomy Observatory (NRAO). To the best of the author’s knowledge, this is first wide bandwidth down-converter at W-band to achieve this high gain and low noise figure among Si/SiGe based systems.

Most everyday AC appliances are designed to operate off of 120V coming from the wall outlet in our homes. This voltage is a standard set from our established infrastructure. Unlike AC devices, DC devices do not have any set standard of voltage they all will run off of. This presents a problem for the DC house as the various loads that will be used will have different required input voltages. One set voltage for a wall outlet will not suffice for the DC House. This Smart Wall Outlet is designed with a DC-DC converter that will have its output voltage controlled by an on-board microprocessor. The Smart Wall Outlet detects current going into a device, and will adjust the voltage applied to the device to ensure it operates most efficiently. Proof of concept research has already been performed in the past, and this thesis will look towards implementing this concept on a single circuit board.

The goals for most of today’s receiver system are sampling at high-speed, with high resolution and with as few errors as possible. This master thesis describes the design of a high-speed sampling system with"state-of-the-art"components available on the market. The system is designed with a parallel Analog-to-digital converter (ADC) architecture, also called time interleaving. It aims to increase the sampling speed of the system. The system described in this report uses four 12-bits ADCs in parallel. Each ADC can sample at 125 MHz and the total sampling speed will then theoretically become 500 Ms/s. The system has been implemented and manufactured on a printed circuit board (PCB). Up to four boards can be connected in parallel to get 2 Gs/s theoretically. In an approach to increase the systems performance even further, a timing error estimation algorithm will be used on the sampled data. This algorithm estimates the timing errors that occur when sampling with non-uniform time interval between samples. After the estimations, the sampling clocks can be adjusted to correct the errors. This thesis is concerning some ADC theory, system design and PCB implementation. It also describes how to test and measure the system’s performance. No measurement results are presented in this thesis because measurements will be done after this project. The last part of the thesis discusses future improvementsto achieve even higher performance.

<p>The goals for most of today’s receiver system are sampling at high-speed, with high resolution and with as few errors as possible. This master thesis describes the design of a high-speed sampling system with"state-of-the-art"components available on the market. The system is designed with a parallel Analog-to-digital converter (ADC) architecture, also called time interleaving. It aims to increase the sampling speed of the system. The system described in this report uses four 12-bits ADCs in parallel. Each ADC can sample at 125 MHz and the total sampling speed will then theoretically become 500 Ms/s. The system has been implemented and manufactured on a printed circuit board (PCB). Up to four boards can be connected in parallel to get 2 Gs/s theoretically. </p><p>In an approach to increase the systems performance even further, a timing error estimation algorithm will be used on the sampled data. This algorithm estimates the timing errors that occur when sampling with non-uniform time interval between samples. After the estimations, the sampling clocks can be adjusted to correct the errors. </p><p>This thesis is concerning some ADC theory, system design and PCB implementation. It also describes how to test and measure the system’s performance. No measurement results are presented in this thesis because measurements will be done after this project. The last part of the thesis discusses future improvementsto achieve even higher performance.</p>

In many systems today sensors or transmitters need to be read or controlled simultaneously. This thesis investigates a new architecture used for deskewing clock signals between multiple separated parts of a signal transmission system. The original application is a multi-channel MEMS transceiver system utilizing beamforming, split into two separate modules. The presented architecture has been developed after evaluating multiple alternative systems. Special focus has been on the locking time of the full system. Furthermore, the scalability for use in implementations with requirements for interconnection delays, as well as input frequency and final timing skew. The full system consists of two parts, a master- and a slave-system. A proof-of-concept transistor implementation has been done in a 180 nm CMOS process. It has been simulated to verify the functionality with varying interconnection delays, i.e., wire lengths up to 1 m. The results from the simulations show that the system works as intended with a skew less than the required 1 ns for a 10 MHz clock signal. This fulfills the requirement for the original application. Further work is required to finalize the presented system before deployment in an actual product