<p>Test Tools are very important in the design of a system. They generally simulate a working environment, only at a higher</p><p>speed, or with less frequently occurring test cases. In the verification of protocols based on the Fibre Channel physical layer,</p><p>this becomes a necessity, as errors can be non-existent or very unusual in normal operating environments. Most systems need</p><p>to be able to handle these unexpected events nonetheless. Therefore, there is a need for a method of introducing these errors</p><p>in a controlled way.</p><p>A bit error generation and logging tool for two proprietary protocols based on the Fibre Channel physical layer has been</p><p>developed. The hardware platform consists mainly of a Virtex II Pro FPGA with accompanying I/O support. Control of the</p><p>hardware is handled by a graphical user interface residing on a PC. Communication between the hardware and the PC is</p><p>handled with a UART. The final implementation can handle four parallel one way links, or two full duplex links,</p><p>independently. This report describes the implementation and the necessary theoretical background for this.</p>

Test Tools are very important in the design of a system. They generally simulate a working environment, only at a higher speed, or with less frequently occurring test cases. In the verification of protocols based on the Fibre Channel physical layer, this becomes a necessity, as errors can be non-existent or very unusual in normal operating environments. Most systems need to be able to handle these unexpected events nonetheless. Therefore, there is a need for a method of introducing these errors in a controlled way. A bit error generation and logging tool for two proprietary protocols based on the Fibre Channel physical layer has been developed. The hardware platform consists mainly of a Virtex II Pro FPGA with accompanying I/O support. Control of the hardware is handled by a graphical user interface residing on a PC. Communication between the hardware and the PC is handled with a UART. The final implementation can handle four parallel one way links, or two full duplex links, independently. This report describes the implementation and the necessary theoretical background for this.

Gemeinsamer Workshop von Universitaetsrechenzentrum und Professur "Rechnernetze und verteilte Systeme" der Fakultaet fuer Informatik der TU Chemnitz. Workshop-Thema: Mobilitaet Dieser Vortrag beschreibt neue Techniken zum Speichern grosser Datenmenge, auch über grosse Entfernungen hinweg.

International Telemetering Conference Proceedings / October 25-28, 1999 / Riviera Hotel and Convention Center, Las Vegas, Nevada / Today’s large-scale signal processing systems impose massive bandwidth requirements on both internal and external communication systems. Most often, these bandwidth requirements are met by scalable input/output architectures built around high-performance, standards-based technology. Several such technologies are available and are in common use as internal and/or external communication mechanisms. This paper provides an overview of some of the more common scalable technologies used for internal and external communications in real-time data acquisition systems. With respect to internal communications mechanisms this paper focuses on three ANSI-standard switched fabric technologies: RACEway (ANSI/VITA 5-1994), SKYchannel (ANSI/VITA 10-1995) and Myrinet (ANSI/VITA 26-1998). The discussion then turns to how Fibre Channel, HiPPI, and ATM are used to provide scalable external communications in real-time systems. Finally, glimpse of how these technologies are evolving to meet tomorrow’s requirements is provided.

International Telemetering Conference Proceedings / October 23-26, 2000 / Town & Country Hotel and Conference Center, San Diego, California / Flexible data multiplexing that supports both low-speed (4 Mbps) to very high-speed output devices (networks and recording systems up to 480 Mbps), along with data network formatting, can greatly enhance the results of range upgrading.

ITC/USA 2007 Conference Proceedings / The Forty-Third Annual International Telemetering Conference and Technical Exhibition / October 22-25, 2007 / Riviera Hotel & Convention Center, Las Vegas, Nevada / This paper describes the integration activities associated with the instrumentation and telemetry system developed for an F/A-18 Hornet Flight Test program, including bench integration, avionics integration, and aircraft ground and flight checkout. The system is controlled by a Boeing Integrated Defense System (IDS) Flight Test Instrumentation designed Instrumentation Control Unit (ICU), which interfaces to an avionics pilot display and Ground Support Unit (GSU) to set up the instrumentation during preflight and control the instrumentation during flight. The system takes in MIL-STD-1553, analog parameters, Ethernet, Fibre Channel, and video, and records these with onboard recorders. Selected subsets of this data may be routed to the telemetry system, which features two RF streams, each of which contains up to four PCM streams combined into a composite by a data combiner. The RF streams are transmitted by multi-mode digital transmitters capable of PCM-FM or Shaped Offset Quadrature Phase Shift Keying (SOQPSK), with selectable Turbo-Product Code (TPC) Forward Error Correction (FEC). This paper describes integration of the system with the IDS Flight Test Integration Test Bench (ITB), production avionics integration facilities, and final aircraft ground checkout and initial flight tests. It describes results of integration activities and bench evaluation of the telemetry system.

International Telemetering Conference Proceedings / October 27-30, 1997 / Riviera Hotel and Convention Center, Las Vegas, Nevada / The purpose of this paper is to describe the development of a very high-speed instrumentation and digital data recording system. The system converts multiple asynchronous analog signals to digital data, forms the data into packets, transmits the packets across fiber-optic lines and routes the data packets to destinations such as high speed recorders, hard disks, Ethernet, and data processing. This system is capable of collecting approximately one hundred megabytes per second of filtered packetized data. The significant system features are its design methodology, system configuration, decoupled interfaces, data as packets, the use of RACEway data and VME control buses, distributed processing on mixedvendor PowerPCs, real-time resource management objects, and an extendible and flexible configuration.

Thesis (M.T.S.C.)--Miami University, Dept. of English, 2003. / Title from first page of PDF document. Includes bibliographical references (p. 105).

This diploma work describes the software-defined network focusing on optical networks. Subsequently designed their own software network that is implemented in the environment OMNeT ++. This work deals with SDN (software-defined network), and impact on current communications environment in the world of telecom-munications services.

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